Profichip VPC3+S - Asynchronous Intel Mode

Pin Description 3
VPC3+S User Manual
Revision 1.04
13
Copyright © profichip GmbH, 2012
The following chapters are describing the different processor interface modes supported by
the VPC3+S. For every interface mode the settings of the configuration pins and the signals
necessary to communicate with the microcontroller are listed. Common signals for all
interface types (like clock divider, interrupt and Profibus interface signals are not explicitly
listed in this overview.
3.2.1 Asynchronous Intel Mode
In Asynchronous Intel Mode the data and address busses are separate
(non-multiplexed). Address line 11 is to be connected to pin C5 of the
VPC3+S.
XREADY mechanism is supported.
Ball
BGA
Pin
QFP
Signal Name
In/Out
Description
Connect to
E3
9
SERMODE
I
‘0’: Parallel Interface
GND
E4
28
MOT/XINT
I
‘0’: Intel Format
GND
D4
33
MODE
I
‘0’: Asynchronous Interface Mode
GND
C5
35
AB11
I
Address Lines Bit 11
CPU Address Bus 11
C2
2
AB10
I
Address Lines Bits [10:0]
CPU
Address Bus [10:0]
B3
44
AB9
I
A1
48
AB8
I(S)
B1
1
AB7
I(S)
C3
45
AB6
I
B2
46
AB5
I
B4
41
AB4
I
A5
38
AB3
I
A6
37
AB2
I
B5
39
AB1
I
B6
36
AB0
I
G4
20
DB7
IO
Data Bus [7:0]
CPU Data Bus [7:0]
H5
23
DB6
IO
H6
24
DB5
IO
G5
22
DB4
IO
G6
25
DB3
IO
F4
21
DB2
IO
F6
27
DB1
IO
F5
26
DB0
IO
C1
3
XCS
I
Chip-Select Signal (active low)
CPU Chip-Select
D5
32
XWR
I
Write Signal (active low)
CPU Write
C6
34
XRD
I
Read Signal (active low)
CPU Read
Figure 3-4: Interface Configuration: Asynchronous Intel Mode