Profichip VPC3+S - Page 30

5 ASIC Interface
30
Revision 1.04
VPC3+S User Manual
Copyright © profichip GmbH, 2012
Mode Register 2, Address 0CH:
bit 7
w-0
4KB_Mode: size of internal RAM
0 = 2K Byte RAM (default).
1 = 4K Byte RAM
bit 6
w-0
No_Check_Prm_Reserved: disables checking of the reserved bits in
DPV1_Status_2/3 of Set_Prm telegram
0 = reserved bits of a Set_Prm telegram are checked (default).
1 = reserved bits of a Set_Prm telegram are not checked.
bit 5
w-0
SYNC_Pol: polarity of SYNC pulse (for Isochronous Mode only)
0 = negative polarity of SYNC pulse (default)
1 = positive polarity of SYNC pulse
bit 4
w-0
SYNC_Ena: enables generation of SYNC pulse (for Isochronous Mode only)
0 = SYNC pulse generation is disabled (default)
1 = SYNC pulse generation is enabled
bit 3
w-0
DX_Int_Port: Port mode for DX_Out interrupt (ignored if SYNC_Ena set)
0 = DX_Out interrupt is not assigned to port DATAEXCH (default).
1 = DX_Out Interrupt (synchronized to SYNCH telegram) is assigned to port
DATAEXCH.
bit 2
w-0
DX_Int_Mode: Mode of DX_out interrupt
0 = DX_Out interrupt is only generated, if Len_Dout_Buf is unequal 0 (default).
1 = DX_Out interrupt is generated after every Data_Exchange telegram
bit 1
w-0
No_Check_GC_Reserved: Disables checking of the reserved bits in
Global_Control telegram
0 = reserved bits of a Global_Control telegram are checked (default).
1 = reserved bits of a Global_Control telegram are not checked.
bit 0
w-1
GC_Int_Mode: Controls generation of New_GC_Command interrupt
0 = New_GC_Command interrupt is only generated, if a changed
Global_Control telegram is received
1 = New_GC_Command interrupt is generated after every Global_Control
telegram (default)
Figure 5-4: Coding of Mode Register 2