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2 Functional Description
8
Revision 1.04
VPC3+S User Manual
Copyright © profichip GmbH, 2012
The MAC status can be observed at any time in the Status Register.
Various events (e.g. various indications, error events, etc.) are entered in
the Interrupt Controller. These events can be individually enabled via a
mask register. Acknowledgement takes place by means of the acknowl-
edge register. The VPC3+S has a common interrupt output.
The integrated Watchdog Timer is operated in three different states:
BAUD_SEARCH, BAUD_CONTROL and DP_CONTROL.
The Micro Sequencer (MS) controls the entire process. It contains the DP-
Slave state machine (DP_SM).
The integrated 4K Byte RAM that operates as a Dual-Port-RAM contains
procedure-specific parameters (buffer pointer, buffer lengths,
Station_Address, etc.) and the data buffers.
In the UART, the parallel data flow is converted into the serial data flow and
vice-versa. The VPC3+S is capable of automatically identifying the baud
rates (9.6 Kbit/s - 12 Mbit/s).
The Idle Timer directly controls the bus times on the serial bus line.
The IsoM-PLL provides high-precision synchronization mechanisms as
defined in the PROFIBUS DPV2 protocol extension.

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