Profichip VPC3+S - Page 84

7 PROFIBUS DP Extensions
84
Revision 1.04
VPC3+S User Manual
Copyright © profichip GmbH, 2012
Clock_Sync-Buffer
Clock_Value_
Status2
bit 7
r-0
ANH: Announcment Hour
0 = no change planned within the next hour
1 = a change of SWT will occur within the next hour
Clock_Value_
Status2
bit 6
r-0
SWT: Summertime
0 = Winter Time
1 = Summer Time
Clock_Value_
Status2
bit 5
r-0
Reserved
Clock_Value_
Status2
bit 4-3
r-00
CR: Accuracy
0 = 1 ms
1 = 10 ms
2 = 100 ms
3 = 1 s
Clock_Value_
Status2
bit 2-1
r-00
Reserved
Clock_Value_
Status2
bit 0
r-0
SYF: Synchronisation Active:
0 = Clock_Value_Time_Event is synchronized
1 = Clock_Value_Time_Event is not synchronized
r-0
Clock_Value_Time_Event:
Same format as defined in IEC 61158-6 is used. Value is stored with the
most significant byte at the lowest address. No address swapping is done
for Intel format.
r-0
Receive_Delay_Time:
Value is stored with the most significant byte in address 12. No address
swapping is done for Intel format.
r-0
Clock_Value_previous_TE:
Same format as defined in IEC 61158-6 is used. Value is stored with the
most significant byte at the lowest address. No address swapping is done
for Intel format.
rw-0
Clock_Sync_Interval:
Value is stored with the most significant byte in address 24. No address
swapping is done for Intel format.
Figure 7-29: Format of the Clock_Sync-Buffer