R8C/20 Group, R8C/21 Group 14. Timers
Rev.2.00 Aug 27, 2008 Page 168 of 458
REJ09B0250-0200
14.3.4 Pulse Output Forced Cutoff
In the output compare function, PWM mode, reset synchronous PWM mode, complementary PWM mode and
PWM3 mode, the TRDIOji output pin can be forcibly set to the programmable I/O port by the INT0
pin input,
and pulse output can be cut off.
The used pins for the output in these functions or modes can function as the output pin of Timer RD when
setting the applicable bit in the TRDOER1 register to 0 (enable Timer RD output). When the PTO bit in the
TRDOER2 register to 1 (INT0
of pulse output forced cutoff signal input enabled), all bits in the TRDOER1
register are set to 1 (disable Timer RD output, the TRDIOji output pin is used as the programmable I/O port)
after “L” is applied to the INT0
pin. The TRDIOji output pin is set to the programmable I/O port after “L” is
applied to the INT0
pin and waiting for 1 to 2 cycles of the Timer RD operation clock (refer to Table 14.11
Timer RD Operation Clocks).
Set as below when using this function:
• Set the pin status (high impedance, “L” or “H” output) with the pulse output forced cutoff by the P2 and
PD2 registers.
• Set the INT0EN bit in the INTEN register to 1 (enable INT0
input) and the INT0PL bit to 0 (one edge).
• Set the PD4_5 bit in the PD4 register to 0 (input mode).
• Set the INT0
digital filter by the INT0F1 to INT0F0 bits in the INTF register.
• Set the PTO bit in the TRDOER2 register to 1 (enable pulse output forced cutoff signal input INT0
).
According to the selection of the POL bit in the INT0IC register and change of the INT0
pin input, the IR bit in
the INT0IC register is set to 1 (interrupt request). Refer to 12. Interrupts for details of interrupts.
To Next Page
Loading...
Need help?
General
