R8C/20 Group, R8C/21 Group 14. Timers
Rev.2.00 Aug 27, 2008 Page 124 of 458
REJ09B0250-0200
14.1.1 Timer Mode
In this mode, the timer counts an internally generated count source (see Table 14.2 Timer Mode
Specifications).
Figure 14.5 shows the TRAIOC Register in Timer Mode.
Figure 14.5 TRAIOC Register in Timer Mode
Table 14.2 Timer Mode Specifications
Item Specification
Count Sources f1, f2, f8, fOCO
Count Operations • Decrement
• When the timer underflows, the contents in the reload register is reloaded and
the count is inherited
Divide Ratio 1/(n+1)(m+1)
n: setting value of TRAPRE register, m: setting value of TRA register
Count Start Condition Write 1 (count starts) to the TSTART bit in the TRACR register
Count Stop Conditions • Write 0 (count stops) to the TSTART bit in the TRACR register
• Write 1 (count forcibly stops) to the TSTOP bit in the TRACR register
Interrupt Request
Generation Timing
When Timer RA underflows [Timer RA interrupt]
INT1
/TRAIO Pin
Function
Programmable I/O port or INT1 interrupt input
TRAO Pin Function
Programmable I/O port
Read from Timer The count value can be read by reading the TRA and TRAPRE registers
Write to Timer • When registers TRAPRE and TRA are written while the count is stopped,
values are written to both the reload register and counter.
• When registers TRAPRE and TRA are written during the count, values are
written to the reload register and counter (refer to 14.1.1.1 Timer Write
Control during Count Operation).
Timer RA I/O Control Registe
Symbol Address After Reset
TRAIOC
0101h 00h
Bit Symbol Bit Name Function RW
INT1/
____
TRAIO select bit 0 : INT1
____
/TRAIO pin (P1_7)
1 : INT1
____
/TRAIO pin (P1_5)
b3 b2
TIOSEL
b1 b0
00
b7 b6 b5 b4
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
00 0
—
(b7-b6)
TEDGSEL
TRAO output enable bit
TRAIO input filter select bits
—
TOPCR RW
TOENA RW
RW
TIPF0
TIPF1
RW
RW
Set to 0 in timer mode
RWTRAIO polarity switch bit
TRAIO output control bit
Set to 0 in timer mode
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