R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface
Rev.2.00 Aug 27, 2008 Page 292 of 458
REJ09B0250-0200
16.2.1 Transfer Clock
A transfer clock can be selected from 7 internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8 and f1/4) and an
external clock.
When using the clock synchronous serial I/O with chip select, set the SCKS bit in the SSMR2 register to 1 and
select the SSCK pin as the serial clock pin.
When the MSS bit in the SSCRH register is set to 1 (operates as master device), an internal clock can be
selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs clocks of the
transfer rate selected in the CKS0 to CKS2 bits in the SSCRH register.
When the MSS bit in the SSCRH register is set to 0 (operates as slave device), an external clock can be selected
and the SSCK pin functions as input.
16.2.1.1 Association between Transfer Clock Polarity, Phase, and Data
Association between transfer clock polarity, phase and data changes according to a combination of the SSUMS
bit in the SSMR2 register and the CPHS and CPOS bits in the SSMR register.
Figure 16.10 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data.
Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register.
When the MLS bit is set to 1, transfer is started from the LSB to MSB. When the MLS bit is set to 0, transfer is
started from the MSB to LSB.
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