R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface
Rev.2.00 Aug 27, 2008 Page 335 of 458
REJ09B0250-0200
16.3.4 Clock Synchronous Serial Mode
16.3.4.1 Clock Synchronous Serial Format
When setting the FS bit in the SAR register to 1, the clock synchronous serial format is used to communicate.
Figure 16.41 shows the Transfer Format of Clock Synchronous Serial Format.
When the MST bit in the ICCR1 register is set to 1, the transfer clock is output from the SCL pin and when the
MST bit is set to 0, the external clock is input.
The transfer data is output between the fall and the following fall of the SCL clock, and data is determined by
the rise of the SCL clock. The MSB-first or LSB-first can be selected for the order of the data transfer by setting
the MLS bit in the ICMR register. The SDA output level can be changed by the SDAO bit in the ICCR2 register
during the transfer standby.
Figure 16.41 Transfer Format of Clock Synchronous Serial Format
SCL
b0
SDA b1 b2 b3 b4 b5 b6 b7
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