Renesas R8C/20

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R8C/20 Group, R8C/21 Group 14. Timers

Rev.2.00 Aug 27, 2008 Page 123 of 458

REJ09B0250-0200

Figure 14.4 TRA Register

Timer RA Register

Symbol Address After Reset

TRA

0104h FFh

(1)

Mode Function Setting Range RW

NOTE:

00h to FFh

When the TSTOP bit in the TRACR register is set to 1, the TRA register is set to FFh.

All Modes

Counts of an underflow of the TRAPRE

Main Page

Default Chapter8
- Table of Contents8
- Overview17
1 Overview18
- Performance Overview18
- Block Diagram20
- Product Information21
- Pin Assignments23
- Pin Functions24
2 Central Processing Unit (CPU)26
- Data Registers (R0, R1, R2 and R3)27
  - Interrupt Enable Flag (I)28
3 Memory29
- R8C/21 Group30
4 Special Function Registers (Sfrs)31
5 Resets37
- Hardware Reset40
- Power-On Reset Function42
- Voltage Monitor 1 Reset43
6 Voltage Detection Circuit44
- VCC Input Voltage50
- Voltage Monitor 1 Reset51
- Voltage Monitor 2 Interrupt and Voltage Monitor 2 Reset52
7 Programmable I/O Ports54
- Effect on Peripheral Functions55
- Port Settings66
- Unassigned Pin Handling77
8 Processor Mode78
10 Clock Generation Circuit80
- XIN Clock87
- On-Chip Oscillator Clocks88
- CPU Clock and Peripheral Function Clock89
- Power Control90
- Notes on Clock Generation Circuit101
11 Protection102
- Interrupts103
- Software Interrupts104
- Special Interrupts105
- Interrupts and Interrupt Vector106
- Interrupt Control108
- INT Interrupt117
  - Inti Input Filter (I = 0 to 3)119
- Key Input Interrupt120
- Address Match Interrupt122
13 Watchdog Timer129
- Count Source Protection Mode Disabled132
- Count Source Protection Mode Enabled133
14 Timers134
- Timer RA136
- Timer RB153
- Timer RD175
- Count Source180
- Timer RD Interrupt265
  - Notes on Timer RD267
- Timer RE273
  - Output Compare Mode274
  - Notes on Timer RE280
15 Serial Interface281
- Clock Synchronous Serial I/O Mode287
  - Polarity Select Function290
  - Continuous Receive Mode291
- Clock Asynchronous Serial I/O (UART) Mode292
  - Bit Rate296
- Notes on Serial Interface297
- Clock Synchronous Serial Interface298
16 Clock Synchronous Serial Interface299
- Clock Synchronous Serial I/O with Chip Select (SSU)299
  - Transfer Clock308
  - SS Shift Register (SSTRSR)310
- Interrupt Requests311
17 Hardware LIN361
- Input/Output Pins362
- Register Configuration363
- Functional Description365
- Notes on Hardware LIN375
18 A/D Converter376
- One-Shot Mode380
- Repeat Mode383
- Sample and Hold386
- A/D Conversion Cycles387
- Internal Equivalent Circuit of Analog Input388
- Output Impedance of Sensor under A/D Conversion389
- Notes on A/D Converter390
19 Flash Memory391
- Memory Map393
- Functions to Prevent Rewriting of Flash Memory396
- Standard Serial I/O Mode416
- Parallel I/O Mode420
- Notes on Flash Memory421
20 Electrical Characteristics424
21 Usage Notes444
- Notes on Interrupts445
  - Changing Interrupt Sources446
  - Changing Interrupt Control Register Contents447
- Notes on Timers448
  - Notes on Timer RB449
- Notes on A/D Converter463
- Notes on Flash Memory464
- Notes on Noise467
22 Notes on On-Chip Debugger468
23 Notes on Emulator Debugger469
Appendix 1. Package Dimensions470
Appendix 2. Connection Examples between Serial Writer and On-Chip Debugging Emulator471
Appendix 3. Example of Oscillation Evaluation Circuit472
- Index473

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