R8C/20 Group, R8C/21 Group 14. Timers
Rev.2.00 Aug 27, 2008 Page 231 of 458
REJ09B0250-0200
Figure 14.93 Registers TRDIER0 to TRDIER1 in Complementary PWM Mode
Timer RD Interrupt Enable Register i (i = 0 or 1)
Symbol Address After Reset
TRDIER0
TRDIER1
0144h
0154h
11100000b
11100000b
Bit Symbol Bit Name Function RW
RWOVIE
—
(b7 - b5)
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Input capture/compare match
interrupt enable bit C
0 : Disable an interrupt (IMIC) by the
IMFC bit
1 : Enable an interrupt (IMIC) by the
IMFC bit
IMIEC RW
RW
Input capture/compare match
interrupt enable bit D
0 : Disable an interrupt (IMID) by the
IMFD bit
1 : Enable an interrupt (IMID) by the
IMFD bit
Overflow/underflow interrupt enable
bit
0 : Disable an interrupt (OVI) by the
OVF and UDF bits
1 : Enable an interrupt (OVI) by the
OVF and UDF bits
RW
IMIEB RW
Input capture/compare match
interrupt enable bit A
0 : Disable an interrupt (IMIA) by the
IMFA bit
1 : Enable an interrupt (IMIA) by the
IMFA bit
Input capture/compare match
interrupt enable bit B
0 : Disable an interrupt (IMIB) by the
IMFB bit
1 : Enable an interrupt (IMIB) by the
IMFB bit
IMIEA
b7 b6 b5 b4 b3 b2
IMIED
b1 b0
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