R8C/20 Group, R8C/21 Group 14. Timers
Rev.2.00 Aug 27, 2008 Page 236 of 458
REJ09B0250-0200
14.3.9.1 Transfer Timing from Buffer Register
• Transfer from the TRDGRD0, TRDGRC1 and TRDGRD1 registers to the TRDGRB0, TRDGRA1 and
TRDGRB1 registers
When the CMD1 to CMD0 bits in the TRDFCR register are set to 10b, the content is transferred when the
TRD1 register underflows.
When the CMD1 to CMD0 bits are set to 11b, the content is transferred at the compare match in the TRD0
and TRDGRA0 registers.
14.3.9.2 A/D Trigger Generation
The compare match in the TRD0 and TRDGRA0 registers and the TRD1 underflow can be used as a
conversion start trigger of the A/D converter. It can be selected by the ADEG and ADTRG bits in the TRDFCR
register.
Also, set the ADCAP bit in the ADCON0 register to 1 (starts in Timer RD).
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