R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface
Rev.2.00 Aug 27, 2008 Page 327 of 458
REJ09B0250-0200
16.3.3.3 Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and
returns an acknowledge signal.
Figure 16.35 and Figure 16.36 show the Operation Timing in Master Receive Mode (I
2
C Bus Interface Mode).
The receive procedure and operation in master receive mode are shown below.
(1) After setting the TEND bit in the ICSR register to 0, switch from master transmit mode to master
receive mode by setting the TRS bit in the ICCR1 register. And set the TDRE bit in the ICSR register to
0.
(2) When performing the dummy-read of the ICDRR register and starting receive, output the receive clock
synchronizing with the internal clock and receive data. The master device outputs the level set by the
ACKBT bit in the ICIER register to the SDA pin at the 9th clock of the receive clock.
(3) The 1-frame data receive is completed and the RDRF bit in the ICSR register is set to 1 at the rise of the
9th clock. At this time, when reading the ICDRR register, the received data can be read and the RDRF
bit is set to 0 simultaneously.
(4) The continuous receive is enabled by reading the ICDRR register every time the RDRF bit is set to 1. If
the 8th clock falls after reading the ICDRR register by the other processes while the RDRF bit is set to
1, the SCL signal is fixed “L” until the ICDRR register is read.
(5) If the following frame is the last receive frame and the RCVD bit in the ICCR1 register is set to 1
(disables the next receive operation) before reading the ICDRR register, the stop condition generation is
enabled after the following receive.
(6) When the RDRF bit is set to 1 at the rise of the 9th clock of the receive clock, generate the stop
condition.
(7) When the STOP bit in the ICSR register is set to 1, read the ICDRR register. And set the RCVD bit to 0
(maintain the following receive operation).
(8) Return to slave receive mode.
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