R8C/20 Group, R8C/21 Group 16. Clock Synchronous Serial Interface
Rev.2.00 Aug 27, 2008 Page 333 of 458
REJ09B0250-0200
16.3.3.5 Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and data, and the slave device returns an
acknowledge signal.
Figure 16.39 and Figure 16.40 show the Operation Timing in Slave Receive Mode (I
2
C Bus Interface Mode).
The receive procedure and operation in slave receive mode are shown below.
(1) Set the ICE bit in the ICCR1 register to 1 (transfer operation enabled). Set the WAIT and MLS bits in
the ICMR register and CKS0 to CKS3 bits in the ICCR1 register (initial setting). Set the TRS and MST
bits in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode.
(2) When the slave address matches at the 1st frame after detecting the start condition, the slave device
outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock.
Since the RDRF bit in the ICSR register is set to 1 simultaneously, perform the dummy-read (the read
data is unnecessary because of showing slave address and R/W
).
(3) Read the ICDRR register every time the RDRF bit is set to 1. If the 8th clock falls while the RDRF bit is
set to 1, the SCL signal is fixed “L” until the ICDRR register is read. The setting change of the
acknowledge signal which returns to master device before reading the ICDRR register reflects the
following transfer frame.
(4) Reading the last byte is performed by reading the ICDRR register as well.
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