Renesas R8C/20 User Manual

R8C/20 Group, R8C/21 Group 18. A/D Converter
Rev.2.00 Aug 27, 2008 Page 363 of 458
REJ09B0250-0200
Figure 18.3 Registers ADCON1, ADCON2, and AD
A/D Control Register 1
(1)
Symbol Address After Reset
ADCON1
00D7h 00h
Bit Symbol Bit Name Function RW
NOTES:
1.
2.
3. When the VCUT bit is set to 1 (connected) from 0 (not connected), w ait for 1 µs or more before starting A/D
conversion.
b3 b2
VCUT
b1 b0
00
Refer to a description of the CKS0 bit in the
ADCON0 register function
b7 b6 b5 b4
—
(b2-b0)
00 0
If the ADCON1 register is rew ritten during A/D conversion, the conversion result is indeterminate.
CKS1 RW
RW
RW
—
(b7-b6)
Reserved Bit
Vref connect bit
(3)
0 : Vref not connected
1 : Vref connected
Set the BITS bit to 0 (8-bit mode) in repeat mode.
Reserved bit Set to 0
8/10-bit mode select bit
(2)
0 : 8-bit mode
1 : 10-bit mode
RW
Set to 0
Frequency select bit 1
BITS RW
A/D Control Register 2
(1)
Symbol Address After Reset
ADCON2 00D4h 00h
Bit Symbol Bit Name Function RW
NOTE:
1.
b0
000
b3 b2 b1
Reserved bit Set to 0
b7 b6 b5 b4
0 : Without sample and hold
1 : With sample and hold
RW
If the ADCON2 register is rew ritten during A/D conversion, the conversion result is indeterminate.
SMP
A/D conversion method select bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
(b7-b4)
—
—
(b3-b1)
RW
A
/D Registe
r
Symbol Address After Reset
AD
00C1h-00C0h Indeterminate
RWFunction
RO
When BITS bit in ADCON1 register is set to 1
(10-bit mode)
When BITS bit in ADCON1 register is set to 0
(8-bit mode)
8 low -order bits in A/D conversion result A/D conversion result
RW
RO
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
2 high-order bits in A/D conversion result When read, its content is indeterminate
b0b7
(b8)
b0
(b15)
b7

Renesas R8C/20 Specifications

General

Brand	Renesas
Model	R8C/20
Category	Control Unit
Language	English