Renesas R8C series

R8C/1A Group, R8C/1B Group 14. Timers
Rev.1.30 Dec 08, 2006 Page 145 of 315
REJ09B0252-0130
Figure 14.28 TCC1 Register
Timer C Control Register 1
Symbol Address After Reset
TCC1
009Bh 00h
Bit Symbol Bit Name Function RW
INT3
_
____
filter select bits
(1)
NOTES :
1.
2.
3.
RW
When the TCC00 bit in the TCC0 register is set to 0 (count stops), rew rite the TCC13 bit.
When the TCC13 bit is set to 0 (input capture mode), set bits TCC12, and TCC14 to TCC17 to 0.
TCC17
TCC16
Compare 1 output mode select
bits
(3)
b7 b6
0 0 : CMP output remains unchanged even
w hen compare 1 is matched.
0 1 : CMP output is inverted w hen compare 1
signal is matched.
1 0 : CMP output is set to “L” w hen compare 1
signal is matched.
1 1 : CMP output is set to “H” w hen compare 1
signal is matched.
When the same value is sampled from the INT3
_
____
pin three times continuously, the input is determined.
b3 b2
0 : No reload
1 : Set TC register to 0000h w hen compare 1
is matched.
b1 b0
TCC11
b7 b6 b5 b4
TCC15
TCC10
TCC13
Compare 0 / capture select
bit
(2)
TCC12
TCC14
RW
Timer C counter reload select
bit
(3)
Compare 0 output mode select
bits
(3)
b5 b4
0 0 : CMP output remains unchanged even
w hen compare 0 is matched.
0 1 : CMP output is inverted w hen compare 0
signal is matched.
1 0 : CMP output is set to “L” w hen compare 0
signal is matched.
1 1 : CMP output is set to “H” w hen compare 0
signal is matched.
RW
b1 b0
0 0 : No filter
0 1 : Filter w ith f1 sampling
1 0 : Filter w ith f8 sampling
1 1 : Filter w ith f32 sampling
0 : Selects capture (input capture mode).
(3)
1 : Selects compare 0 output.
(output compare mode)
RW
RW
RW