Renesas R8C series

R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface
Rev.1.30 Dec 08, 2006 Page 173 of 315
REJ09B0252-0130
Figure 16.3 SSCRL Register
SS Control Register L
(4)
Symbol Address After Reset
SSCRL
00B9h 01111101b
Bit Symbol Bit Name Function RW
NOTES :
1.
2.
3.
4. Refer to
16.2.8.1 Accessing Registers Associated with Clock Synchronous Serial I/O with Chip Select
for
more information.
Do not w rite to the SOL bit during data transfer.
The data output after serial data is output can be changed by w riting to the SOL bit before or after transfer. When
w riting to the SOL bit, set the SOLP bit to 0 and the SOL bit to 0 or 1 simultaneously by the MOV instruction.
Registers SSCRH, SSCRL, SSMR, SSER, SSSR, SSMR2, SSTDR, and SSRDR.
SOL
Serial data output value
setting bit
When read
0 : The serial data output is set to “L”.
1 : The serial data output is set to “H”.
When w ritten,
(2,3)
0 : The data output is “L” after the serial data output.
1 : The data output is “H” after the serial data output.
RW
—
(b6)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
—
(b7)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
—
—
(b3-b2)
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
—
SOLP
SOL w rite protect bit
(2)
The output level can be changed by the SOL bit w hen
this bit is set to 0.
Cannot w rite to this bit. When read, the content is 1.
RW
b7 b6 b5 b4 b3 b2 b1 b0
—
(b0)
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
SRES
Clock synchronous
serial I/O with chip
select control part
reset bit
When this bit is set to 1, the clock synchronous serial
I/O w ith chip select control block and SSTRSR register
are reset.
The values of the registers
(1)
in the clock synchronous
serial I/O w ith chip select register are maintained.
RW