Renesas R8C series

R8C/1A Group, R8C/1B Group 16. Clock Synchronous Serial Interface
Rev.1.30 Dec 08, 2006 Page 175 of 315
REJ09B0252-0130
Figure 16.5 SSER Register
SS Enable Register
(1)
Symbol Address After Reset
SSER
00BBh 00h
Bit Symbol Bit Name Function RW
NOTE :
1.
0 : Disables transmit end interrupt request.
1 : Enables transmit end interrupt request.
RW
Receive enable bit 0 : Disables receive.
1 : Enables receive.
Transmit enable bit 0 : Disables transmit.
1 : Enables transmit.
0 : Disables receive data full and overrun
error interrupt request.
1 : Enables receive data full and overrun
error interrupt request.
Receive interrupt enable bit
RW
RE
TE
TEIE
Transmit end interrupt enable bit
RW
RIE
TIE
Transmit interrupt enable bit 0 : Disables transmit data empty interrupt
request.
1 : Enables transmit data empty interrupt
request.
Conflict error interrupt enable bit 0 : Disables conflict error interrupt request.
1 : Enables conflict error interrupt request.
—
(b2-b1)
Nothing is assigned. If necessary, set to 0.
When read, the content is 0.
RW
RW
RW
—
b7 b6 b5 b4
Ref er to
16.2.8.1 Accessing Registers Associated with Clock Synchronous Serial I/O with Chip Select
for
more information.
b0b3 b2 b1
CEIE