RH850/F1K Series Hardware Design Guide
R01AN2911EJ0100 Rev. 1.00 Page 4 of 46
Aug 04, 2016
Table of Figures
Figure 1 RH850/F1K Power supply architecture ............................................................................................... 7
Figure 2 RH850/F1K Power up/down timing ................................................................................................... 10
Figure 3 Principle capacitor placement at REGVCC for EMI at data flash operation ..................................... 11
Figure 4 Minimum external components for RH850/F1K (176pin) for normal operation mode ...................... 12
Figure 5 Recommended main oscillator circuit ............................................................................................... 15
Figure 6 Recommended sub oscillator circuit.................................................................................................. 16
Figure 7 Minimum RESET circuit .................................................................................................................... 17
Figure 8 External RESET timing ...................................................................................................................... 18
Figure 9 RESETOUT pin behavior at OPBT0[9] = 1 ....................................................................................... 20
Figure 10 RESETOUT pin behavior at OPBT0[9] = 0 ..................................................................................... 20
Figure 11 Analog Filter Function ..................................................................................................................... 21
Figure 12 ADC conversion time ....................................................................................................................... 27
Figure 13 ADC equivalent input circuit ............................................................................................................ 28
Figure 14 ADC external circuit on analog input ............................................................................................... 29
Figure 15 RH850/F1K 1pin Low-pin debug interface connection .................................................................... 32
Figure 16 RH850/F1K 4pin Low-pin debug interface connection .................................................................... 33
Figure 17 RH850/F1K Nexus, 4pin LPD and 1pin LPD debug interface connection ...................................... 34
Figure 18 RH850/F1K PG-FP5 flash programming interface connection ....................................................... 37
Figure 19 RH850/F1K E1 flash programming interface connection ................................................................ 38
Figure 20 RH850/F1K Combined debug and flash programming interface connections ................................ 39
Figure 21 RH850/F1K Debug and flash programming interface connections when the HSOSC is used as
clock supply ..................................................................................................................................................... 40
Figure 22 Circuit configuration for hot plug-in.................................................................................................. 42
Figure 23 Boundary scan connection of RH850/F1K ...................................................................................... 43