Siemens CPU 948 - Page 108

Logic operations
(continued)
I 6.0
I 6.3
I 6.2
Q 2.1
Output Q 2.1 is "1" when input I 6.0 or input I 6.1 and one
of the inputs I 6.2 or I 6.3 has signal state "1"
Output Q 2.1 is "0" when input I 6.0 has signal state "0"
and the AND condition is not satisfied
I 6.1
&
I 6.0 I 6.1 I 6.2 I 6.3
Q 2.1
I 6.0 I 6.2 I 6.3
I 6.1
Q 2.1
A
I 6.0
O
O I 6.2
= Q2.1
A
I 6.1
O I 6.3
)
I 6.0
I 6.1
I 6.2
I 6.3
Q 2.1
&
1
1
1
1
A (
Logical/circuit diagram
STEP 5 representation
Ladder Control system
Statement
list
OR-before-AND operation
/1st example
diagram flowchart
OR-before-AND operation
I 1.4 I 2..0
I 1.5
Q 3.0
Output Q 3.0 is "1" when both OR conditions are satisifed
I 1.4
I 1.5
Q 3.0
I 2.1
I 2.0
I 2.1
I 1.4 I 1.5
Q 3.0
I 2.0 I 2.1
&
I 2..0
I 1.4
Q3.0
I 2.1
I 1.5
O
I 1.4
O
O
I 1.5
I 2.1
= Q3.0
)
O I 2.0
)
&
1
1 1
A (
1
A (
Logical/circuit diagram
STEP 5 representation
Ladder diagram Control system
Statement
list
/2nd example
flowchart
Output Q 3.0 is "0" when at least one OR condition is not satisfied
Programming Examples in the STL, LAD and CSF Methods of Representation
CPU 948 Programming Guide
3 - 36 C79000-G8576-C848-04