2 Functions
210
7SA522 Manual
C53000-G1176-C155-3
Figure 2-93 Logic diagram of the I>> stage
Definite Time
Overcurrent
Stage I>
The logic of the overcurrent stage I> is the same as that of the I>> stages. In all refer-
ences ,SK!! must merely be replaced with ,SK! or. ,!!3,&.83 with ,!. In
all other respects Figure 2-93 applies.
Inverse Time
Overcurrent
Stage Ip
The logic of the inverse overcurrent stage also in principal functions the same as the
remaining stages. However, the time delay is calculated here based on the type of the
set characteristic, the intensity of the current and a time multiplier (following figure). A
pre-selection of the available characteristics was already done during the configura-
tion of the protection functions. Furthermore, an additional constant time delay 7,S
$GG or 7,S$GG may be selected, which is added to the inverse time. The possible
characteristics are shown in the Technical Data.
The following figure shows the logic diagram. The setting parameter addresses of the
IEC characteristics are shown by way of an example. In the configuration notes (Sub-
section 2.11.3) the different setting addresses are elaborated upon.
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