THEORY OF OPERATATION
RES/ and ∅2-IN come from the Generator, otherwise, the Translator Microprocessor is a totally
independent system. It cannot operate independently however, because all user I/O i.e. Keyboard
and Display, is provided by the Generator, via the GEN/TRANS COMM port. This port is part
of VIA U33. For a description of the operation of the COMM port see [3] GENERATOR VIAS.
In addition U33 provides the data (SRD) and clock (SRC) to set-up shift registers located in
U23.
U26, pins 6 and 14, inverts the LOS/ signal from the AGC and provides LOS (Loss of Signal to
U33 where it is monitored.
The heart of the decoder is a look-up table in U27, a ROM . U27 is addressed by the ROM
address counters and the output of the forward flip-flop located in U23. The ROM address
counters in U23 are synchronized by FS.
A left/right shift register in U23 is used to convert the code to binary data. SREN occurs at the
correct time to discern whether the code bit is a zero or a one. SREN is so spaced (in time) that
the data shifted produces a group BCD (in the case of most codes) at SR outputs TDB0-TDB7.
When a group has been assembled, U27 outputs Byte Ready Enable (TBREN). TBREN is
synchronized and then input to U31, a Versatile Interface Adapter (VIA). TBRDY latches the
time data into the VIA. It also latches U27 outputs TBA0-TBA3 into the VIA. TBA0-TBA3 are
validating bits. When these bits are latched, the VIA issues an interrupt to the Microprocessor
which then performs the firmware part of the decoding process.
Once per frame, U27outputs Frame Ready Enable (TFREN). This signal is used to generate FRP
which is on-time with the input code (in the forward direction). FRP is used by the
Microprocessor and is also output to the PLD U23, where it synchronizes the Translator Pulse
Rates and, in Synchronized Generator modes, the Generator.
TRA11-TRA14 select the correct table (according to code and direction) in U27. This data is
serially entered into U23 from the VIA U33.
VIA U31 serves various additional functions not previously discussed. ZAD is an input to both
CA2 and PB6. At carrier rates of lKHz and lower CA2 causes an increment of Minor Time. For
faster rates, PB6 counts ZAD down, as appropriate, then increments Minor Time. FWD is sensed
at PB4 to inform the Microprocessor of the code direction. SHIFT/ is a test output, which
initializes many binary devices.
Symmetricom, Inc. TM7000 TymMachine TCG/T (Rev D) 4-13
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