TDK-Lambda GH10-100 - Page 10

5.1.3.8 Abort .......................................................................................... 133
5.1.4 Sequencer Setting Memory ...................................................................... 134
5.2 Trigger System ........................................................................................................ 134
5.2.1 Trigger Initialize ........................................................................................ 134
5.2.2 Trigger In ................................................................................................... 135
5.2.3 Trigger Out ................................................................................................ 135
5.2.4 Trigger Delay ............................................................................................. 135
5.3 Sequencer + Trigger System Examples ................................................................... 136
5.3.1 WAVE Mode Voltage Programming via Communication Example ........... 136
5.3.2 WAVE Mode Execution via Communication Example .............................. 136
5.3.3 WAVE Mode Execution via Front Panel Example ..................................... 136
5.3.4 LIST Mode Example ................................................................................... 137
5.3.5 WAVE Mode Example ............................................................................... 138
5.4 Internal Resistance ................................................................................................. 139
5.5 Constant Power Limit ............................................................................................. 140
5.6 Preload Control ...................................................................................................... 141
5.7 OCL – Analog Programming Over Current Limit .................................................... 142
5.7.1 OCL Example (10Volts, 500Amperes supply) ............................................ 142
5.8 Slew-Rate Control .................................................................................................. 143
5.9 Advanced Parallel ................................................................................................... 144
5.9.1 Advanced Parallel Connection (System Assembly) ................................... 144
5.9.2 Advanced Parallel Dis-Connection (System Dis-Assembly) ...................... 144
5.9.3 Load Connection ....................................................................................... 144
5.9.4 Advanced Parallel System Acknowledge .................................................. 146
5.9.4.1 Acknowledge via the front panel ............................................... 146
5.9.4.2 Acknowledge via communication .............................................. 146
5.9.4.3 Acknowledge via communication (Blank Panel master power
supply) ................................................................................................... 146
5.9.5 Advanced Parallel operation .................................................................... 147
5.9.6 Slave units operation in Advanced Parallel connection ........................... 147
5.9.7 Advanced Parallel fault system ................................................................. 147
5.9.8 Advanced Parallel Errors ........................................................................... 147
5.9.9 Advanced Parallel system identification (*idn?) ...................................... 148
5.9.10 Advanced Parallel memory settings ......................................................... 148
5.9.10.1 Single or Master roles non-volatile memory parameters .......... 148
5.9.10.2 Slave role non-volatile memory parameters ............................. 150
5.10 Communication Watchdog .................................................................................... 152
5.10.1 Activated Communication Watchdog Timeout ........................................ 152
5.11 Boolean Commands Return Value ......................................................................... 153
CHAPTER 6: STATUS, FAULT AND SRQ REGISTERS .............................................................. 154
6.1 General ................................................................................................................... 154
6.2 SCPI Language ........................................................................................................ 154
6.2.1 SCPI Register Tree ..................................................................................... 154
6.2.2 Questionable Condition (Fault Register) Group Structure ....................... 155
6.2.3 Operational Condition (Status Register) Group Structure ........................ 156
6.2.4 Standard Event Status Group Structure ................................................... 157
6.2.5 Output Queue ........................................................................................... 158
6.2.6 Error Queue .............................................................................................. 158