DISPLAY
PR
!OR
I
2
GATE
I
OR
4
VARIABLE
VARIABLE
HOLDOFF
SWEEP
HOLOOFF
Figure 3-7. Readout display priorities.
Figure 3-7
and
causes no interference with the displayed
waveforms. If the Readout circuitry
is
able to display
all
the required readout dots during the holdoff time between
sweeps, the prioritizer U2985 will turn off the Dot Start
Governor until the next subframe of readout information
is
to
be
displayed.
When
the sweep times are either too fast
to finish a readout display during holdoff (at 5
ns
per divi-
sion
no
identifiable holdoff time exists) or too slow to allow
flicker-free readout, readout display modes other than
priority one are initiated.
The
next most desirable time for dots to
be
displayed
is
during "triggerable" time: that time between sweeps when
the oscilloscope
is
waiting for a sweep trigger event to
occur. This is designated priority two
and
may
cause slight
interference
on
the leading
edge
of the displayed trace if a
dot is
being
displayed when the actual trigger occurs.
Finally, the least desirable dot display time is during a
waveform trace display. This display time is designated
either priority three or priority four. (Priority four indicates
a higher demand of display time.)
In
priorities three
and
four, dot displays occur during the
main
portion of the
waveform display. However, the waveform blanking asso-
ciated with these displays
is
relatively random
in
nature
and
is
usually not noticeable.
To start a readout display, the ROSFRAME (readout
subframe) request from the Timing Logic (diagram
1)
clocks the Q output of flip-flop U2850A
HI.
ROSFRAME
is
a periodic clocking signal used to hold the overall
refresh rate constant
and
occurs at regular intervals,
regardless of the state of the display.
As the Dot Cycle Generator
runs,
it resets half of
U2830
in
the Dot Timer at somewhat irregular intervals
with the ST ARTDOT signal
(via
inverter U2890A).
The
Dot
Timer then starts a timing sequence,
and
the rising edge
of the
REFRESH
signal from U2830 pin 4 clocks the
latched ROSFRAME request from U2850A
pin
5 to the Q
output
(pin
9)
of flip-flop U2850B. This
HI,
applied to the
Theory of
Operation-2445A/2455A
Service
S 1 input
(pin
10)
of prioritizer U2985, sets it
up
to incre-
ment with the next REFRESH clock applied to its clock
input
(pin
11
).
The
LO
Q output of U28508
(pin
8)
applied
to the reset input of U2850A resets the latched ROS-
FRAME request.
See
Figure 3-8 for
an
illustration of the
timing sequence involved.
The
next
REFRESH
clock increments the display prior-
ity to
one
by clocking a
HI
to the Q
0
output
(pin
12)
of
prioritizer shift register U2985. (Table 3-7 illustrates the
operation of U2985.)
The
same clock latches the now
LO
ROSFRAME request at U2850B
pin
12
to the a output
(pin
9),
where it
is
applied to the
S1
input
(pin
10) of priori-
tizer U2985.
The
LO
on
the
S1
input of the prioritizer will
remain until another ROSFRAME request from the Timing
Logic occurs,
and
the encoded priority at the output pins
of U2985 will
remain
as
it
Is
presently set.
As
each
of the consecutive dots of the readout frame
are displayed, the Dot
and
Character Counters increment
until
all
dots of the subframe have
been
displayed (eight
characters). As the Character Counter increments to
address the next character of the display (first character of
the next frame), the fourth bit of counter U2940 goes
HI
and
sets the
SO
input
(pin
9)
of prioritizer U2985
HI
via
exclusive-OR-gate U2990A.
The
Dot Timer then clocks the
prioritizer with a
REFRESH
clock
on
pin
11
of U2985,
and
the priority is decremented back to zero (indicating that
the subframe
is
completed).
The
next ROSFRAME request
starts the process over again to display the next subframe
of readout display.
The
sequence just described
is
the
priority one display mode
and
is
used when holdoff time
between sweeps allows
all
dots of the subframe to
be
displayed before the next ROSFRAME request occurs.
If a second ROSFRAME request occurs before the
Character Counter indicates the
end
of the subframe (to
decrement the prioritizer back to zero), input
S1
of U2985
will
be
set
HI
(while the
SO
input pin remains
LO)
and
the
Table 3-7
Operation of Prioritizer Shift Register
Select Inputs
Mode
so
S1
H H
Parallel Load
H
L L
QA (decrease priority)
L
H H
QD(increase priority)
L
L
Hold
Data
3-31
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