Theory of Operation-2445A/2455A Service
10
MHz
REFRESH
(625
KHzl
ROSFRAME
U2850A-5
LO
UNTIL
NEXT
SUBFRAME
REQUEST
U2850B-9
(S1
l
(
INCREMENT
ENABLE)
U2850B-8
SETS
PRIORITIZER
TO
INCREMENT
*INCREMENTS
PRIORITIZER
*NOTE
IF
S0
IS
ALSO
HI
AT
THIS
TIME,
THE
PRIORITY
DOES
NOT
CHANGE.
3831-06
Figure 3-8. Timing of Refresh Prioritizer.
Prioritizer will increment to priority two (outputs Oc
and
0
0
go
HI)
on
the next STARTDOT cycle. If this display
priority still
is
inadequate to complete the subframe display
before the next ROSFRAME request occurs, priority two
will
be
incremented up
to
priority three, or even
to
priority
four should the condition persist. Priority four
is
operation-
ally the same
as
priority three, but it
is
used to keep the
readout circuitry continuously displaying readout data on
through the next subframe, thus allowing the display to
catch
up.
If priority four
is
in
effect, the next decrement
that occurs at the
end
of a subframe only returns the
prioritizer to priority three, not to priority two.
The circuit composed of flip-flop U2950A
and
exclusive-OR-gate U2990A enables either edge of the CA3
bit to decrement the priority of the display when a sub-
frame
is
completed. Either a negative or positive transition
on
pin
2
of
U2990A will cause the output at
pin
3 go
HI
since the Q output of U2950A
is
still at the opposite level.
The
HI
from U2990A indicates that the
end
of the present
subframe has occurred,
and
it sets
up
the prioritizer to
decrement with the next
REFRESH
clock. At the same
time that the prioritizer decrements, the changed
level
of
the CA3 bit
is
clocked through U2950A
and
causes the
output of exclusive-OR-gate U2990A
to
return
LO
until the
next subframe
is
completed.
If the subframe
is
completed
(SO
on
U2985 goes
HI)
when a ROSFRAME request
is
also pending
(S1
is
also
3-32
HI),
U2985 does a parallel load, reloading the present
priority back into the prioritizer. Since,
in
this case, the
subframe display was completed at the same rate
as
the
ROSFRAME request occurred, the readout display priority
is
not changed.
Dot Start Governor
The Dot Start Governor detects the display priority
from the Refresh Prioritizer and initiates dot-display cycles
as the appropriate conditions are met. The conditions
tested include display priority, sweep gate completion, dot
completion, readout control status,
and
the readout active
enable from the Display Sequencer.
When
the readout board status line (ACTIVE/
ADDRESSABLE )
is
HI
(signifying display)
and
the REST
line goes
HI
to indicate that the dot cycle
is
complete,
AND-gate U2970C generates a
HI
at
pin
8 (DOTOK) to
signal that a new dot display
is
allowed. The
HI
from
U2970C enables most of the gating
in
the Dot Start
Governor. If the Refresh Prioritizer has encoded a display
priority of either one or two, the output of exclusive-OR-
gate U29908
is
HI.
When
DOTOK from U2970C goes
HI
to enable a dot display, the
LO
reset from
pin
6 of U2970B
to
pin
1 of flip-flop U2880A
is
removed. Now, when the A
Sweep gate ( SGA ) goes
HI
(beginning of Holdoff), the
HI
at the D input of U2880A is clocked to the Q output
and
the Q output at pin 6 will go
LO,
requesting display of a
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