priority one or two dot. This
LO
dot request is propagated
through U2885B, U2890D, U2890B,
and
U2890C and sets
the STARTDOT signal
LO.
STARTDOT going
LO
resets
Dot Cycle Generator shift register U2995
and
counter
U2830B
of
the Dot Timer. Resetting the Dot Cycle Gen-
erator shift register causes the REST signal from U2995
pin 13
to
go
to
a
LO,
removing the
HI
DOTOK signal at
U2970C pin
8.
As
DOTOK goes LO, STARTDOT at pin 8
of U2890C goes
HI
to start the DOT Cycle Generator. At
the same time the reset to U2880A is asserted via
U2970B and the dot request is removed. Both the Dot
Timer and the Dot Cycle Generator are now enabled
and
start the first dot-display cycle during holdoff time.
After the Display Sequencer U650 (diagram
5)
has time
to respond to the end
of
the sweep gate,
it
sets the
readout active signal (
1mA
) to pin 4 of U2880A
LO.
This
sets
pin
5
of
U2855B LO, and the signal is propagated
through U2855B, U2890D, U2890B, and U2890C, as
before, resetting the Dot Timer
and
the Dot Cycle Genera-
tor. REST then goes
LO
as before
and
starts the Dot
Cycle Generator and Dot Timer. This cycle continues,
displaying one dot per cycle (except for the first non-
displayed dot
of
a character which is automatically initiated
by
EOCH2
, until the Display Sequencer determines that
the readout time
is
over (sets ROA HI) or until the display
priority is decremented
to
zero.
When a display priority
of
three or four exists, the out-
put
of
U2990B
will
be LO,
and
U2970B, U2880A, and the
associated logic gates following it will not be able
to
ini-
tiate a dot cycle.
In
either
of
these display priorities,
U29700, U2835C, U2980A, U2965B,
and
flip-flop U2950B
detect the higher priority
and
generate a readout request
signal ( ROA ) to the Display Sequencer. The
LO
from
U2950B pin 8 propagates through U2890B and U2890C
to
initiate a ST ARTDOT cycle. When the Display Sequencer
recognizes that the readout request signal is
LO,
it will
perform the mode-dependent setup functions necessary
to
give display control to the Readout Board and will then set
the ROA (readout active) line LO. The
LO
will
be
clocked
into U2880B, and the Dot Cycle Generator will generate a
GETDOT signal, resetting the readout request from flip-
flop U2950B. Only one dot is displayed for each readout
request.
A similar readout display request will
be
generated
when priority-two-or-higher displays
are
required when
sweep gates are not present (dot display during triggerable
time after holdoff). This condition is detected by NANO-
gate U2885A. AND-gate U2970D allows a readout request
to
be
generated when
in
the interfere mode. This mode is
only invoked during a single-sequence waveform display
and ensures that
all
of
the selected sweep combinations
are displayed once, followed by a complete readout frame
(for the purpose of crt photography).
Theory
of Operation-2445A/2455A Service
Dot Cycle Generator
The Dot Cycle Generator, composed
of
shift register
U2995, flip-flop U2880B, and associated gating circuitry,
generates time-related signals for the following purposes:
unbJanking
the crt to display a dot; requesting the next
byte of dot data
in
preparation for displaying the next dot;
and
reenabling itself
to
repeat the tasks, via the Dot Start
Governor (dependent on the display priority).
The timing relationships
of
the Dot Cycle Generator
output signals
are
controlled by shift register U2995. When
the Dot Start Governor initiates a ST ART DOT cycle as
previously described, the STARTDOT signal initially goes
LO, resetting
all
the Q outputs
of
U2995
LO
and
setting
the Q output
of
flip-flop U2880B to a
HI.
The STARTDOT
signal is then returned HI, and the Dot Timer counter
U2830A and shift register U2995 are enabled. The shift
register begins to consecutively shift
HI
logic levels
to
its Q
output pins with each 5-MHz clock from the Dot Timer.
After approximately 400 ns, pin 5
(Qc) of the shift register
will go
HI.
The
HI
at
Oc propagates through exclusive-
OR-gate U2990D and AND-gate U2970A to unblank the
crt by setting the readout blanking signal ( ROB )
HI.
When the
QF
output
of
U2995 goes
HI
(1
µs after
ST ART
DOT),
the output
of
U2990D goes
LO
and the out-
put
of
U2990C goes HI. The
LO
from U2990D propagates
through U2970A to blank the crt ( ROB goes
LO)
and to
clock flip-flop U2880B via NANO-gate U2980C. The
ffi5A
(readout active) level from the Display Sequencer (diagram
5)
is clocked from the D input (pin 12)
of
U2880B to the Q
output; and, if
LO
(indicating that the readout circuitry had
control of the crt when unblanking occurred; thus the dot
was displayed), the output
of
U2980B is set HI. With three
HI
levels applied to NANO-gate U2885C, a GETDOT
request is generated to get the next byte
of
dot-position
data for display. The next 5-MHz clock sets the
QG output
of
U2995 HI, and the output
of
U2990C goes
LO,
remov-
ing the
LO
GETDOT signal.
At 1.4
µ5
after STARTDOT goes
HI
, U2995 pin 13
(QH)
goes
HI
to produce the REST signal, indicating that the
current dot cycle is complete and the Dot Cycle Generator
is
at REST. If the readout ACTIVE/ ADDRESSABLE mode
bit at U2970C pin 10 is still HI, the REST signal going
HI
produces a
HI
DOTOK signal (next dot
is
allowed) at pin
8.
This
HI
applied to pin 10
of
U2890C, along with any
of
the
possible dot requests from the Dot Start Governor, will ini-
tiate another ST ART DOT cycle for the next dot
of
the
display. As long as the Display Sequencer holds the
readout active
line
( ROA )
LO,
U2885B, U2890D, and
U2890B
of
the Dot Start Governor will automatically ini-
tiate dot cycles as soon as the previous one ends (REST
goes
HI),
until the Refresh Prioritizer is decremented to
zero.
3-33
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