Theory
of
Operation-2445A/2455A Service
When
the last dot of the character
is
called from the
Character
ROM,
the rncR' bit
(DD7)
applied to latch
U2905 at
pin
18
(in
the Vertical Character
DAC
circuitry) is
LO.
At the
end
of that dot displdccycle, the
GETDOT
sig-
nal
(going
HI)
clocks the
LO
E H bit into latch U2905
and
increments character counter U2940. The latched bit
becomes the
rncRT signal
(end
of character, delayed one
dot request)
and
is
applied to U2885B, along with the
already
LO
EOCH
bit, to reset Dot Counter U2870. The
least-significant bits to the Character
ROM
address pins
(AO
through
A4)
are
then zeros,
and
the first dot of the
next character is addressed,
The
Horizontal
and
Vertical
DACs don't write this first dot position data into their
registers until the
end
of the next GETDOT signal. That
same
GETDOT
signal also clocks
EOCH1
into U2905
which becomes
EOCH2
at
pin
6
(end
of character, delayed
by
two dot requests). rncR2
is
applied to AND-gate
U2970A
and
disables the gate prior to the time the Dot
Cycle Generator attempts to unblank the crt for the first
dot display; thus the first dot of a character
is
never
displayed.
Disabling the unblanking path for the first dot of each
character
in
the manner just described allows the more
radical voltage changes between characters to settle
before the actual display of the next character begins.
When
the dot data for one of these undisplayed dots also
has the
EOCH
bit set
LO,
it
is
a space character,
and
the
display is advanced to the next character.
Dot Timer
The Dot Timer, composed of U2890A
and
U2830, gen-
erates three, time-related signals used to synchronize the
display
and
maintain the proper sequencing of the indi-
vidual character dots.
The two least-significant bits of the Dot Timer, from
U2830 pins
11
and
10, are reset at the beginning of a dot
cycle
by
a
LO
ST ARTDOT signal applied to the reset input
of the counter
via
U2890A. As the dot-display cycle
begins, the ST ARTDOT signal returns
HI
and
the Dot
Timer begins counting
in
a binary fashion.
The
10-MHz
clock applied to
pin
13 is divided
by
two to produce the 5-
MHz clocking signal at output pin
11.
The 5-MHz clock
sequences the Dot Cycle Generator through the various
phases of the dot-display cycle. The
REFRESH
output
signal from U2830
pin
4 updates the Refresh Prioritizer as
each
subframe
is
displayed.
A third clock, from U2830 pin
6,
occurs at approxi-
mately þÿ8 ¼sintervals and allows any pending dot requests
to generate a
ROA
signal to the Display Sequencer
via
flip-flop U2950B. (Readout request generation
is
described
in
the Dot Start Governor discussion.)
3-34
HIGH VOLTAGE POWER SUPPLY
AND CRT
The High-Voltage Supply
and
CRT circuit (diagram
8)
provides the voltage levels
and
control circuitry for opera-
tion of the cathode-ray tube (crt). The circuitry consists of
the
High
Voltage Oscillator, the
High
Voltage Regulator,
the Cathode Supply, the Anode Multiplier, the
DC
Re-
storer, Focus Amplifiers, the CRT
and
the various CRT
Control circuits.
High-Voltage Oscillator
The High-Voltage Oscillator transforms power obtained
from the
-15
volt unregulated supply to the various
ac
levels necessary for the operation of the crt circuitry. The
circuit consists of transformer T1970, switching transistor
01981,
and
associated circuitry. The low-voltage oscilla-
tions set up
in
the primary winding of T1970
are
raised
by
transfotmer action to high-voltage levels
in
the secondary
windings. These
ac
secondary voltages are applied to the
DC
Restorer, the Cathode Supply, and the anode multi-
plier circuits.
Oscillation occurs due to the positive feedback from the
primary winding
(pin
4 to
pin
5)
to the smaller base-drive
winding
(pin
3 to
pin
6)
for transistor 01981.
The
fre-
quency of oscillation is about
50
kHz,
and
is determined
primarily
by
the resonant frequency of the transformer.
When
power
is
first applied, the High-Voltage Regulator
circuit detects that the negative
crt cathode voltage
is
too
positive
and
pulls
pin
2 of transformer T1970 negative.
The negative
level
forward biases transistor 01981
via
the
base-drive winding of the transformer. Current begins to
flow
in
the primary winding through transistor 01981,
inducing a magnetic field around the transformer primary
winding.
The
increasing magnetic field induces a current
in
the base-drive winding that further increases the base
drive to the transistor. This in-phase feedback causes
current
in
01981 to increase until the primary winding
current reaches its maximum
value.
As the rate of change
of the primary current peaks
and
then reverses, the
induced magnetic field begins to decay. This decreases the
base-drive current
and
begins turning
Q1981
off.
As 01981
is
beginning to turn off, the magnetic field
around the primary winding continues
to
collapse at the
resonant frequency rate
of
the transformer. This induces
into the base-drive winding a voltage that completely turns
off the transistor.
The
collapsing magnetic field goes to
zero. then builds in the opposite direction to a maximum
before collapsing
again
(resonant flywheel effect). This
sequence of events occurs repetitively
as
the circuit con-
tinues to oscillate.
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