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Timer 3 and Timer 4 Registers
T3CCTL0 (0xCC) – Timer 3 Channel 0 Capture/Compare Control
Bit Name Reset R/W Description
7 – 0 R0 Reserved
6
IM
1 R/W Channel 0 interrupt mask
0: Interrupt is disabled.
1: Interrupt is enabled.
5:3
CMP[2:0]
000 R/W Channel 0 compare output mode select. Specified action occurs on output when timer value
equals compare value in T3CC0
000: Set output on compare
001: Clear output on compare
010: Toggle output on compare
011: Set output on compare-up, clear on 0
100: Clear output on compare-up, set on 0
101: Set output on compare, clear on 0xFF
110: Clear output on compare, set on 0x00
111: Initialize output pin. CMP[2:0] is not changed.
2
MODE
0 R/W Mode. Select Timer 3 channel 0 mode
0: Capture mode
1: Compare mode
1:0
CAP[1:0]
00 R/W Capture mode select
00: No capture
01: Capture on rising edge
10: Capture on falling edge
11: Capture on both edges
T3CC0 (0xCD) – Timer 3 Channel 0 Capture/Compare Value
Bit Name Reset R/W Description
7:0
VAL[7:0]
0x00 R/W Timer capture/compare value channel 0. Writing to this register when T3CCTL0.MODE=1 (compare
mode) causes the T3CC0.VAL[7:0] update to the written value to be delayed until
T3CNT.CNT[7:0]=0x00.
129
SWRU191C–April 2009–Revised January 2012 Timer 3 and Timer 4 (8-Bit Timers)
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