Peripheral I/O
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Table 7-1. Peripheral I/O Pin Mapping (continued)
P0 P1 P2
Periphery/
Function
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 4 3 2 1 0
Alt. 2 TX RX RT CT
USART 1 SPI MI M0 C SS
Alt. 2 MI M0 C SS
USART 1
RX TX RT CT
UART
Alt. 2 RX TX RT CT
TIMER 1 4 3 2 1 0
Alt. 2 3 4 0 1 2
TIMER 3 1 0
Alt. 2 1 0
TIMER 4 1 0
Alt. 2 1 0
32-kHz XOSC Q1 Q2
DEBUG DC DD
OBSSEL 5 4 3 2 1 0
7.6.1 Timer 1
PERCFG.T1CFG selects whether to use alternative 1 or alternative 2 locations.
In Table 7-1, the Timer 1 signals are shown as the following:
• 0: Channel 0 capture/compare pin
• 1: Channel 1 capture/compare pin
• 2: Channel 2 capture/compare pin
• 3: Channel 3 capture/compare pin
• 4: Channel 4 capture/compare pin
P2DIR.PRIP0 selects the order of precedence when assigning several peripherals to Port 0. When set to
10, Timer 1 channels 0–1 have precedence, and when set to 11, Timer 1 channels 2–3 have precedence.
To have all Timer 1 channels visible in the alternative 1 location, move both USART 0 and USART 1 to
the alternative 2 location.
P2SEL.PRI1P1 and P2SEL.PRI0P1 select the order of precedence when assigning several peripherals
to Port 1. The Timer 1 channels have precedence when the former is set low and the latter is set high.
7.6.2 Timer 3
PERCFG.T3CFG selects whether to use alternative 1 or alternative 2 locations.
In Table 7-1, the Timer 3 signals are shown as the following:
• 0: Channel 0 capture/compare pin
• 1: Channel 1 capture/compare pin
P2SEL.PRI2P1 and P2SEL.PRI3P1 select the order of precedence when assigning several peripherals
to Port 1. The Timer 3 channels have precedence when both bits are set high. If P2SEL.PRI2P1 is set
high and P2SEL.PRI3P1 is set low, the Timer 3 channels have precedence over USART 1, but USART 0
has precedence over the Timer 3 channels as well as over USART 1.
7.6.3 Timer 4
PERCFG.T4CFG selects whether to use alternative 1 or alternative 2 locations.
In Table 7-1, the Timer 4 signals are shown as the following:
• 0: Channel 0 capture/compare pin
84
I/O Ports SWRU191C–April 2009–Revised January 2012
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