Output Compare Mode
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NOTE: Before an I/O pin can be used by the timer, the required I/O pin must be configured as a
Timer 1 peripheral pin.
The channel input pin is synchronized to the internal system clock. Thus, pulses on the input pin must
have a minimum duration greater than the system clock period.
The content of the 16-bit capture register is read out from registers T1CCnH:T1CCnL.
When the capture takes place, the interrupt flag for the channel, T1STAT.CHnIF (n is the channel
number), is set. An interrupt request is generated if enabled, see Section 9.10 for details.
9.8 Output Compare Mode
In output compare mode, the I/O pin associated with a channel is set as an output. After the timer has
been started, the contents of the counter are compared with the contents of the channel compare register
T1CCnH:T1CCnL. If the compare register equals the counter contents, the output pin is set, reset, or
toggled, according to the compare output mode setting of T1CCTLn.CMP. Note that all edges on output
pins are glitch-free when operating in a given output compare mode. Writing to the compare register
T1CCnL is buffered, so that a value written to T1CCnL does not take effect until the corresponding
high-order register, T1CCnH, is written. Writing to compare registers T1CCnH:T1CCnL does not take effect
on the output compare value until the counter value is 0x00.
Note that channel 0 has fewer output compare modes because T1CC0H:T1CC0L has a special function in
modes 6 and 7, meaning these modes would not be useful for channel 0.
When a compare occurs, the interrupt flag for the channel, T1STAT.CHnIF (n is the channel number), is
set. An interrupt request is generated if enabled, see Section 9.10 for details.
Examples of output compare modes in various timer modes are given in the following figures.
Edge-aligned: PWM output signals can be generated using the timer modulo mode and channels 1 and 2
in output compare mode 6 or 7 (defined by the T1CCTLn.CMP bits, where n is 1 or 2) as shown in
Figure 9-4. The period of the PWM signal is determined by the setting in T1CC0, and the duty cycle is
determined by T1CCn, where n is the PWM channel, 1 or 2.
The timer free-running mode may also be used. In this case, CLKCONCMD.TICKSPD and the prescaler
divider value in the T1CTL.DIV bits set the period of the PWM signal. The polarity of the PWM signal is
determined by whether output compare mode 6 or 7 is used.
PWM output signals can also be generated using output compare modes 4 and 5 as shown in Figure 9-4,
or by using modulo mode as shown in Figure 9-5. Using output compare mode 4 or 5 is preferred for
simple PWM.
Center-aligned: PWM outputs can be generated when the timer up/down mode is selected. The channel
output compare mode 4 or 5 (defined by T1CCTLn.CMP bits, where n is 1 or 2) is selected, depending on
the required polarity of the PWM signal. The period of the PWM signal is determined by T1CC0, and the
duty cycle for the channel output is determined by T1CCn, where n is the PWM channel, 1 or 2.
The center-aligned PWM mode is required by certain types of motor-drive applications, and typically less
noise is produced than in the edge-aligned PWM mode, because the I/O pin transitions are not lined up on
the same clock edge.
In some types of applications, a defined delay or dead time is required between outputs. Typically, this is
required for outputs driving an H-bridge configuration to avoid uncontrolled cross-conduction in one side of
the H-bridge. The delay or dead-time can be obtained in the PWM outputs by using T1CCn as shown in
the following:
Assuming that channel 1 and channel 2 are used to drive the outputs using timer up/down mode and the
channels use output compare modes 4 and 5, respectively, then the timer period (in Timer 1 clock
periods) is:
t
P
= T1CC0 × 2
and the dead time, i.e., the time when both outputs are low, (in Timer 1 clock periods) is given by:
t
D
= T1CC1 – T1CC2
110
Timer 1 (16-Bit Timer) SWRU191C–April 2009–Revised January 2012
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