RF Core
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25.1 RF Core
The RF core contains several submodules that support and control the analog radio modules. In addition,
it provides an interface between the MCU and the radio which makes it possible to issue commands, read
status, and automate and sequence radio events.
The link-layer engine (LLE) controls the RF transceiver state and most of the dynamically controlled
analog signals such as power up / down of analog modules. The LLE is used to provide the correct
sequencing of events (such as performing an FS calibration before enabling the receiver). It handles
packet assembly and decoding, including automatic length field handling, address insertion and filtering
and CRC generation and checking.
The radio data RAM holds a FIFO for transmit data (Tx FIFO) and a FIFO for receive data (Rx FIFO).
Both FIFOs are 128 bytes long and have hardware control of pointers when data is entered and removed
from the FIFOs. In addition, the RAM contains six segments of 128 bytes, one of which is used for
communication with the LLE.
The bit-stream processor is used for whitening and de-whitening transferred signals and CRC
generation and check.
The modulator transforms raw data into I/Q signals to the transmitter DAC.
The demodulator is responsible for retrieving the over-the-air data from the received signal.
The frequency synthesizer (FS) generates the carrier wave for the RF signal.
25.2 Interrupts
The radio is associated with two interrupt vectors on the CPU. These are the RFERR interrupt (interrupt
0) and the RF interrupt (interrupt 12) with the following functions.
• RFERR: Error situations in the radio are signaled using this interrupt.
• RF: Interrupts coming from normal operation are signaled using this interrupt.
The RF interrupt vector combines the interrupts in RFIF. Note that these RF interrupts are rising-edge
triggered. Thus, an interrupt is generated when, e.g., the SFD status flag goes from 0 to 1. The RFIF
interrupt flags are described in Section 25.2.1.
25.2.1 Interrupt Registers
Two main interrupt-control SFR registers are used to enable the RF and RFERR interrupts. These are the
following:
• RFERR: IEN0.RFERRIE
• RF: IEN2.RFIE
Two main interrupt-flag SFR registers hold the RF and RFERR interrupt flags. These are the following:
• RFERR: TCON.RFERRIF
• RF:S1CON.RFIF
The two interrupts generated from the RF core are a combination of several sources within the RF core.
Each of the individual sources has its own enable and interrupt flags in RF core. Flags can be found in
RFIRQF0, RFIRQF1, and RFERRF. Interrupt enable masks can be found in RFIRQM0, RFIRQM1, and
RFERRM.
The interrupt enable bits in the mask registers are used to enable individual interrupt sources. Note that
masking an interrupt source does not affect the updating of the corresponding status in the flag registers.
Due to the use of individual interrupt masks in the RF core, the interrupts coming from the RF core have
two-layered masking, and care must be taken when processing these interrupts. The procedure is
described as follows.
292
CC2541 Proprietary Mode Radio SWRU191C– April 2009–Revised January 2012
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