Texas Instruments CC253x - 16-Bit Counter; Timer 1 Operation; Free-Running Mode

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8.8 DMA Registers
This section describes the SFR registers associated with the DMA controller.
DMAARM (0xD6) – DMA Channel Arm
Bit Name Reset R/W Description
7
ABORT
0 R0/W DMA abort. This bit is used to stop ongoing DMA transfers. Writing a 1 to this bit aborts all
channels which are selected by setting the corresponding DMAARM bit to 1.
0: Normal operation
1: Abort all selected channels
6:5 – 00 R/W Reserved
4
DMAARM4
0 R/W1 DMA arm channel 4
This bit must be set in order for any DMA transfers to occur on the channel. For nonrepetitive
transfer modes, the bit is automatically cleared on completion.
3
DMAARM3
0 R/W1 DMA arm channel 3
This bit must be set in order for any DMA transfers to occur on the channel. For nonrepetitive
transfer modes, the bit is automatically cleared on completion.
2
DMAARM2
0 R/W1 DMA arm channel 2
This bit must be set in order for any DMA transfers to occur on the channel. For nonrepetitive
transfer modes, the bit is automatically cleared on completion.
1
DMAARM1
0 R/W1 DMA arm channel 1
This bit must be set in order for any DMA transfers to occur on the channel. For nonrepetitive
transfer modes, the bit is automatically cleared on completion.
0
DMAARM0
0 R/W1 DMA arm channel 0
This bit must be set in order for any DMA transfers to occur on the channel. For nonrepetitive
transfer modes, the bit is automatically cleared on completion.
DMAREQ (0xD7) – DMA Channel Start Request and Status
Bit Name Reset R/W Description
7:5 – 000 R0 Reserved
4
DMAREQ4
0 R/W1 H0 DMA transfer request, channel 4
When set to 1, activate the DMA channel (has the same effect as a single trigger event). This bit
is cleared when DMA transfer is started.
3
DMAREQ3
0 R/W1 H0 DMA transfer request, channel 3
When set to 1, activate the DMA channel (has the same effect as a single trigger event). This bit
is cleared when DMA transfer is started.
2
DMAREQ2
0 R/W1 H0 DMA transfer request, channel 2
When set to 1, activate the DMA channel (has the same effect as a single trigger event). This bit
is cleared when DMA transfer is started.
1
DMAREQ1
0 R/W1 H0 DMA transfer request, channel 1
When set to 1, activate the DMA channel (has the same effect as a single trigger event). This bit
is cleared when DMA transfer is started.
0
DMAREQ0
0 R/W1 H0 DMA transfer request, channel 0
When set to 1, activate the DMA channel (has the same effect as a single trigger event). This bit
is cleared when DMA transfer is started.
DMA0CFGH (0xD5) – DMA Channel-0 Configuration Address High Byte
Bit Name Reset R/W Description
7:0
DMA0CFG[15:8]
0x00 R/W The DMA channel-0 configuration address, high-order
DMA0CFGL (0xD4) – DMA Channel-0 Configuration Address Low Byte
Bit Name Reset R/W Description
7:0
DMA0CFG[7:0]
0x00 R/W The DMA channel 0 configuration address, low-order
104
DMA Controller SWRU191C– April 2009–Revised January 2012
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