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Texas Instruments CC253x - Timer 1; Timer 3; Peripheral IO Pin Mapping

Texas Instruments CC253x
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Chapter 7
SWRU191CApril 2009 Revised January 2012
I/O Ports
There are 21 digital input/output pins that can be configured as general-purpose digital I/O or as peripheral
I/O signals connected to the ADC, timers, or USART peripherals. The use of the I/O ports is fully
configurable from user software through a set of configuration registers.
The I/O ports have the following key features:
21 digital input/output pins
General-purpose I/O or peripheral I/O
Pullup or pulldown capability on inputs
External interrupt capability
The external interrupt capability is available on all 21 I/O pins. Thus, external devices may generate
interrupts if required. The external interrupt feature can also be used to wake the device up from sleep
mode (power modes PM1/PM2/PM3).
Topic ........................................................................................................................... Page
7.1 Unused I/O Pins ................................................................................................ 82
7.2 Low I/O Supply Voltage ...................................................................................... 82
7.3 General-Purpose I/O .......................................................................................... 82
7.4 General-Purpose I/O Interrupts ........................................................................... 82
7.5 General-Purpose I/O DMA ................................................................................... 83
7.6 Peripheral I/O .................................................................................................... 83
7.7 Debug Interface ................................................................................................. 86
7.8 32-kHz XOSC Input ............................................................................................ 86
7.9 Radio Test Output Signals .................................................................................. 86
7.10 Power-Down Signal MUX (PMUX) ........................................................................ 86
7.11 I/O Registers ..................................................................................................... 87
81
SWRU191CApril 2009Revised January 2012 I/O Ports
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