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USART Registers
U0UCR (0xC4) – USART 0 UART Control
Bit Name Reset R/W Description
7
FLUSH
0 R0/W1 Flush unit. When set, this event stops the current operation and returns the unit to the idle state.
6
FLOW
0 R/W UART hardware flow enable. Selects use of hardware flow control with RTS and CTS pins
0: Flow control disabled
1: Flow control enabled
5
D9
0 R/W
If parity is enabled (see PARITY, bit 3 in this register), then this bit sets the parity level as follows:
0: Odd parity
1: Even parity
4
BIT9
0 R/W Set this bit to 1 in order to enable the parity bit tranfer (as 9th bit). The content of this 9th bit is given
by D9, if parity is enabled by PARITY.
0: 8-bit transfer
1: 9-bit transfer
3
PARITY
0 R/W
UART parity enable. One must set BIT9 in addition to setting this bit for parity to be calculated.
0: Parity disabled
1: Parity enabled
2
SPB
0 R/W UART number of stop bits. Selects the number of stop bits to transmit
0: 1 stop bit
1: 2 stop bits
1
STOP
1 R/W UART stop-bit level must be different from the start-bit level
0: Low stop bit
1: High stop bit
0
START
0 R/W UART start-bit level. Ensure that the polarity of the start bit is opposite the level of the idle line.
0: Low start bit
1: High start bit
U0GCR (0xC5) – USART 0 Generic Control
Bit Name Reset R/W Description
7
CPOL
0 R/W SPI clock polarity
0: Negative clock polarity
1: Positive clock polarity
6
CPHA
0 R/W SPI clock phase
0:
Data is output on MOSI when SCK goes from CPOL inverted to CPOL, and data input
is sampled on MISO when SCK goes from CPOL to CPOL inverted.
1: Data is output on MOSI when SCK goes from CPOL to CPOL inverted, and data input
is sampled on MISO when SCK goes from CPOL inverted to CPOL.
5
ORDER
0 R/W Bit order for transfers
0: LSB first
1: MSB first
4:0
BAUD_E[4:0]
0 0000 R/W
Baud rate exponent value. BAUD_E along with BAUD_M determines the UART baud rate and
the SPI master SCK clock frequency.
U0DBUF (0xC1) – USART 0 Receive/Transmit Data Buffer
Bit Name Reset R/W Description
7:0
DATA[7:0]
0x00 R/W USART receive and transmit data. When writing this register, the data written is written to the
internal transmit-data register. When reading this register, the data from the internal read-data
register is read.
U0BAUD (0xC2) – USART 0 Baud-Rate Control
Bit Name Reset R/W Description
7:0
BAUD_M[7:0]
0x00 R/W
Baud-rate mantissa value. BAUD_E along with BAUD_M decides the UART baud rate and the
SPI master SCK clock frequency.
169
SWRU191C–April 2009–Revised January 2012 USART
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