Texas Instruments CC253x - Page 168

USART Registers www.ti.com
• UxGCR, USART x generic control
• UxDBUF, USART x receive/transmit data buffer
• UxBAUD, USART x baud-rate control
U0CSR (0x86) – USART 0 Control and Status
Bit Name Reset R/W Description
7
MODE
0 R/W USART mode select
0: SPI mode
1: UART mode
6
RE
0 R/W UART receiver enable. Note: Do not enable receive before UART is fully configured.
0: Receiver disabled
1: Receiver enabled
5
SLAVE
0 R/W SPI master or slave mode select
0: SPI master
1: SPI slave
4
FE
0 R/W0
UART framing error status. This bit is automatically cleared on a read of the U0CSR register or bits
in the U0CSR register.
0: No framing error detected
1: Byte received with incorrect stop-bit level
3
ERR
0 R/W0
UART parity error status. This bit is automatically cleared on a read of the U0CSR register or bits in
the U0CSR register.
0: No parity error detected
1: Byte received with parity error
2
RX_BYTE
0 R/W0 Receive byte status. UART mode and SPI slave mode. This bit is automatically cleared when
reading U0DBUF; clearing this bit by writing 0 to it effectively discards the data in U0DBUF.
0: No byte received
1: Received byte ready
1
TX_BYTE
0 R/W0 Transmit byte status. UART mode and SPI master mode
0: Byte not transmitted
1: Last byte written to data-buffer register has been transmitted
0
ACTIVE
0 R USART transmit/receive active status. In SPI slave mode, this bit equals slave select.
0: USART idle
1: USART busy in transmit or receive mode
168
USART SWRU191C–April 2009–Revised January 2012
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