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DMA Memory Access
Table 8-2. DMA Configuration Data Structure (continued)
Byte
Bit Name Description
Offset
6 6:5
TMODE[1:0]
The DMA channel transfer mode
00: Single
01: Block
10: Repeated single
11: Repeated block
6 4:0
TRIG[4:0]
Selects one of the triggers shown in Table 8-1
7 7:6
SRCINC[1:0]
Source address increment mode (after each transfer):
00: 0 bytes/words
01: 1 byte/word
10: 2 bytes/word
11: –1 byte/word
7 5:4
DESTINC[1:0]
Destination address increment mode (after each transfer):
00: 0 bytes/words
01: 1 byte/word
10: 2 bytes/words
11: –1 byte/word
7 3
IRQMASK
Interrupt mask for this channel.
0: Disable interrupt generation
1: Enable interrupt generation on DMA channel done
7 2
M8
Mode of 8th bit for VLEN transfer length; only applicable when WORDSIZE = 0 and VLEN
differs from 000 and 111.
0: Use all 8 bits for transfer count
1: Use 7 LSB for transfer count
7 1:0
PRIORITY[1:0]
The DMA channel priority:
00: Low, CPU has priority.
01: Assured, DMA at least every second try
10: High, DMA has priority
11: Reserved
103
SWRU191C–April 2009–Revised January 2012 DMA Controller
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