Texas Instruments CC253x

To Next Page

To Previous Page

Appendix C

SWRU191C–April 2009– Revised January 2012

References

References and other useful material:

1. IEEE Std. 802.15.4-2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY)

specifications for Low Rate Wireless Personal Area Networks (LR-WPANs)

http://standards.ieee.org/getieee802/download/802.15.4-2006.pdf

2. CC2530 Data Sheet (SWRS081)

3. CC2531 Data Sheet (SWRS086)

4. CC2533 Data Sheet (SWRS087)

5. CC2540 Data Sheet (SWRS084)

6. CC2541 Data Sheet (SWRS110)

7. Bluetooth® Core Technical Specification document, version 4.0

https://www.bluetooth.org/technical/specifications/adopted.htm

8. Universal Serial Bus Revision 2.0 specification http://www.usb.org/developers/docs/usb_20_101111.zip

367

SWRU191C–April 2009–Revised January 2012 References

Submit Documentation Feedback

Main Page

Default Chapter2
- Table of Contents2
Preface14
- Cc253X Family Overview15
- Register Bit Conventions16
Introduction17
- Overview18
- Cc253X Block Diagram18
- CC2540 Block Diagram19
- CC2541 Block Diagram20
8051 Cpu24
- 8051 CPU Introduction25
- Memory25
  - Memory Map25
- XDATA Memory Space (Showing SFR and DATA Mapping)26
- CODE Memory Space26
- CODE Memory Space for Running Code from SRAM26
  - CPU Memory Space27
  - Physical Memory28
- SFR Overview29
- Overview of XREG Registers32
- Instruction Set Summary37
  - Interrupts40
- Instructions that Affect Flag Settings40
  - Interrupt Masking41
- Interrupts Overview41
- Interrupt Overview43
  - Interrupt Processing45
  - Interrupt Priority47
- Priority Level Setting48
- Interrupt Priority Groups48
- Interrupt Polling Sequence49
Debug Interface50
- Debug Mode51
- Debug Communication51
- External Debug Interface Timing51
- Transmission of One Byte51
- Typical Command Sequence-No Extra Wait for Response52
  - Debug Commands53
- Typical Command Sequence. Wait for Response53
  - Debug Configuration55
  - Debug Status55
- Burst Write Command (First 2 Bytes)55
  - Hardware Breakpoints56
- Pm_Active56
  - Flash Programming57
    - Lock Bits57
  - Debug Interface and Power Modes57
- Flash Lock-Protection Bit Structure Definition57
  - Registers59
Power Management and Clocks60
- Power Management Introduction61
- Power Modes61
- Pcon_Idle62
  - Power-Management Registers63
- Clock System Overview65
Reset70
- Power-On Reset and Brownout Detector71
- Clock-Loss Detector71
Flash Controller72
- Flash Memory Organization73
- Flash Write73
- Example Write Sequence74
  - CPU Flash Write75
  - Flash75
- Flash Write Using DMA75
I/O Ports78
- Unused I/O Pins79
- Low I/O Supply Voltage79
- General-Purpose I/O79
- General-Purpose I/O Interrupts79
- General-Purpose I/O DMA80
- Peripheral I/O80
  - Timer 181
  - Timer 381
- Peripheral I/O Pin Mapping81
DMA Controller92
- DMA Operation93
- DMA Operation94
  - DMA Configuration Parameters95
- Variable Length (VLEN) Transfer Options96
- DMA Trigger Sources98
- DMA Configuration-Data Structure99
  - DMA Registers101
Timer 1 (16-Bit Timer)103
- 16-Bit Counter104
- Timer 1 Operation104
- Free-Running Mode104
- Modulo Mode105
- Up-And-Down Mode105
- Channel-Mode Control105
- Input Capture Mode106
- Output Compare Mode106
- Initial Compare Output Values (Compare Mode)107
- Output Compare Modes, Timer Free-Running Mode108
- Output Compare Modes, Timer Modulo Mode109
- Output Compare Modes, Timer Up-And-Down Mode110
  - IR Signal Generation and Learning111
    - Introduction111
    - Modulated Codes111
- Frequency Error Calculation for 38-Khz Carrier111
  - Non-Modulated Codes112
- Block Diagram of Timers in IR-Generation Mode112
- Modulated Waveform Example112
- IR Learning Board Diagram113
  - Timer 1 Registers114
  - Accessing Timer 1 Registers as Array119
Timer 3 and Timer 4 (8-Bit Timers)120
- 8-Bit Timer Counter121
- Timer 3 and Timer 4 Mode Control121
- Channel Mode Control121
- Input Capture Mode122
- Output Compare Mode122
- Timer 3 and Timer 4 Interrupts122
- Initial Compare Output Values (Compare Mode)122
  - Timer 3 and Timer 4 DMA Triggers123
  - Timer 3 and Timer 4 Registers123
Sleep Timer128
- General129
- Timer Compare129
- Timer Capture129
- Sleep Timer Registers130
- Sleep Timer Capture (Example Using Rising Edge on P0_0)130
Adc132
- ADC Introduction133
- ADC Operation133
  - ADC Inputs133
- ADC Block Diagram133
Battery Monitor139
- Functionality and Usage of the Battery Monitor140
- Using the Battery Monitor for Temperature Monitoring140
- Values Showing How Different Temperatures Relate to BATTMON_VOLTAGE for a Typical Device140
  - Battery Monitor Registers141
- Values for a and B (for a Typical Device) When Using the Battery Monitor for Temperature Monitoring141
Random-Number Generator143
- Introduction144
- Random-Number-Generator Operation144
- Basic Structure of the Random-Number Generator144
  - Random-Number-Generator Registers145
AES Coprocessor146
- AES Operation147
- Key and IV147
- Padding of Input Data147
- Interface to CPU147
- Modes of Operation147
- Cbc-Mac147
- CCM Mode148
- Message Authentication Phase Block B0148
- Authentication Flag Byte148
- Message Encryption Phase Block149
- Encryption Flag Byte149
Watchdog Timer152
- Watchdog Mode153
- Timer Mode153
- Watchdog Timer Register153
Usart155
- UART Mode156
- SPI Mode157
  - SPI Master Operation157
  - SPI Slave Operation158
- SSN Slave-Select Pin158
- Baud-Rate Generation158
- Commonly Used Baud-Rate Settings for 32 Mhz System Clock158
Operational Amplifier164
- Description165
- Calibration165
- Clock Source165
- Registers165
Analog Comparator166
- Description167
- Register167
- Analog Comparator167
  - Operation169
20 I C169
- Block Diagram of the I169
- Bit Transfer on I171
  - Bus171
  - Module 7-Bit Addressing Format171
- C Module Addressing Format with Repeated START Condition171
- Slave Transmitter Mode172
- Slave Receiver Mode173
- Master Transmitter Mode175
- Master Receiver Mode176
  - C Clock Generation and Synchronization177
- Arbitration Procedure between Two Master Transmitters177
  - Clock Generators During Arbitration177
  - C Registers178
- Miscellaneous States178
- Clock Rates Defined at 32 Mhz179
USB Controller181
- USB Introduction182
- USB Enable182
- 48-Mhz USB PLL182
- USB Controller Block Diagram182
- USB Interrupt Flags Interrupt-Enable Mask Registers183
- IN and out Fifos186
- FIFO Sizes for EP186
Timer 2 (MAC Timer)197
- Timer Operation198
- Interrupts199
- Event Outputs (DMA Trigger and Radio Events)200
- Timer Start-And-Stop Synchronization200
- Timer 2 Registers202
- Internal Registers203
Cc253X Radio208
- RF Core209
  - Interrupts209
  - Interrupt Registers209
- FIFO Access213
- Dma213
- Memory Map213
  - Rxfifo214
  - Txfifo214
  - Frame-Filtering and Source-Matching Memory Map214
- Frame Filtering and Source Matching Memory Map214
  - Frequency and Channel Programming215
  - IEEE 802.15.4-2006 Modulation Format215
- Modulation216
- I/Q Phases When Transmitting a Zero-Symbol Chip Sequence, T216
- IEEE 802.15.4-2006 Symbol-To-Chip Mapping216
  - IEEE 802.15.4-2006 Frame Format217
    - MAC Layer217
    - PHY Layer217
- Schematic View of the IEEE 802.15.4 Frame Format217
- Format of the Frame Control Field (FCF)217
  - Transmit Mode218
- Frame Data Written to the TXFIFO219
- TX Flow220
  - Transmitted Frame Processing221
  - Synchronization Header221
  - Frame-Length Field221
  - Frame Check Sequence221
- Single Transmitted Frame221
- Transmitted Synchronization Header221
  - Interrupts222
  - Clear-Channel Assessment222
  - Output Power Programming222
  - Tips and Tricks222
  - Receive Mode222
    - RX Control222
- FCS Hardware Implementation222
  - RX State Timing223
  - Received-Frame Processing223
- Single Received Frame and Transmitted Acknowledgment Frame223
  - Synchronization Header and Frame-Length Fields224
  - Frame Filtering224
- SFD Signal Timing224
- Filtering Scenarios (Exceptions Generated During Reception)226
  - Source Address Matching227
- Matching Algorithm for Short and Extended Addresses228
- Interrupts Generated by Source Address Matching229
  - Frame-Check Sequence230
  - Acknowledgement Transmission230
- Data in RXFIFO for Different Settings230
- Acknowledge Frame Format230
- Acknowledgment Timing231
- Command Strobe Timing231
  - RXFIFO Access232
- Behavior of FIFO and FIFOP Signals233
  - Link Quality Indication234
  - Radio-Control State Machine234
- Main FSM235
  - Random-Number Generation236
- FFT of the Random Bytes236
- FSM State Mapping236
  - Packet Sniffing and Radio Test Output Signals237
- Histogram of 20 Million Bytes Generated with the RANDOM Instruction237
  - Command Strobe Processor238
- Running a CSP Program240
  - Instruction Set Summary241
- Instruction Set Summary242
  - Instruction Set Definition243
  - Registers255
- Register Overview255
  - Register Settings Update256
  - Register Access Modes256
- Example Hardware Structure for the R* Register Access Mode256
- Registers that Require Update from Their Default Value256
- Register-Bit Access Modes256
  - Register Descriptions257
CC2540 and CC2541 Bluetooth Low Energy Radio275
- Registers276
CC2541 Proprietary Mode Radio278
- RF Core279
- Interrupts279
  - Interrupt Registers279
- RF Core Data Memory280
- Radio RAM280
  - Fifos281
- Mapping of Radio Memory to MCU XDATA Memory Space281
- FIFO Pointers281
- Commands to FIFO Via RFST Register283
- Access to FIFO Registers283
  - Dma284
  - RAM-Based Registers285
- Address Structure for Auto Mode289
- Address Structure for Basic Mode290
  - Variables in RAM291
  - Bit-Stream Processor291
    - Whitening291
- RAM-Based Registers in RAM291
  - CC2500-Compatible PN9 Whitening292
- PN7 Whitening292
  - Crc293
- CC2500-Compatible Whitening293
- CRC Module294
- Register Settings for Different Crcs294
  - Coprocessor Mode295
- Register Settings for some Commonly Used Crcs, Assuming Initialization with All 1S295
  - Frequency and Channel Programming296
  - Modulation Formats296
  - Receiver296
- Supported Modulation Formats, Data Rates, and Deviations296
  - Packet Format297
- Air Interface Packet Format for Basic Mode297
- Air Interface Packet Format for Auto Mode298
- Bits of 9-Bit Header298
- Bits of 10-Bit Header298
  - RX FIFO Packet Organization299
- Structure of Packets in the RX FIFO299
  - TX FIFO Packet Organization300
  - TX Buffers for ACK Payload300
- Structure of Packets in the TX FIFO300
- Segments for Holding ACK Payload for each Address Entry300
  - Link Layer Engine301
    - Command Register302
    - Radio Tasks302
- Commands from MCU to LL Engine Via RFST Register302
- Timer 2 Capture Settings304
- End-Of-Task Causes304
- Recommended RAM Register Settings for Start Tone306
- Interrupt and Counter Operation for Received Messages307
- Interrupt and Counter Operation for Received Messages308
- End-Of-Receive Tasks310
- Interrupt and Counter Operation for Received ACK Packets312
- End-Of-Transmit Tasks313
- Additional Reasons for End-Of-Transmit on Clear-Channel Tasks315
- Timing of Packets in RX Tasks316
  - RF Test Commands317
- Timing of Packets in TX Tasks317
  - Random Number Generation318
  - Packet Sniffing319
- Complete Appended Packet319
- Packet-Sniffer Modes of Operation319
  - Registers320
    - Register Overview320
- XREG Register Overview320
  - Register Settings Update321
- Registers that Should be Updated from Their Default Value, Bit Rates 1 Mbps and Lower321
- Registers that Should be Updated from Their Default Value, Bit Rate 2 Mbps321
  - SFR Register Descriptions322
Voltage Regulator342
Available Software343
- Smartrf™ Software for Evaluation (Www.ti.com/Smartrfstudio)344
- Remoti™ Network Protocol (Www.ti.com/Remoti)344
- Simpliciti™ Network Protocol (Www.ti.com/Simpliciti)345
- TIMAC Software (Www.ti.com/Timac)345
- Z-Stack™ Software (Www.ti.com/Z-Stack)346
- BLE Stack Software346
A Abbreviations347
B Additional Information350
- Texas Instruments Low-Power RF Web Site351
- Low-Power RF Online Community351
- Texas Instruments Low-Power RF Developer Network351
- Low-Power RF Enewsletter351
C References352
Revision History353
- Important Notice354

Texas Instruments CC253x - Page 367

Table of Contents

Related product manuals