www.ti.com
J721E EVM Hardware Architecture
35
SPRUIS4A–December 2019–Revised May 2020
Submit Documentation Feedback
Copyright © 2019–2020, Texas Instruments Incorporated
Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
4.5.3 DDR I/O Voltage Selection
There is a DIP switch provided on the J721E SoM to select the SoC’s DDR and LPDDR4 memory I/O
supply for the LPDDR4/LPDDR4x.
Currently, the J721E device does not support LPDDR4x. This support may be added at a later date. The
EVM does support this feature if/when support is added to the silicon.
The DIP switch SW1 Bit 1 provides an option to change the logic of D Flip-Flop (U7) that controls the
Load Switches TPS22965TDSGRQ1 and TPS22976NDPUT to decide the I/O supply voltages.
Table 19. DDR I/O Voltage Selection
SW1 Bit 1 SDRAM_TYPE Selected DDR I/O Voltage
LOW LPDDR4X 0.6V
HIGH LPDDR4 1.1V
Figure 21. LPDDR4 IO Voltage Selection Circuit
To Next Page
Loading...
