J721E EVM Hardware Architecture
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SPRUIS4A–December 2019–Revised May 2020
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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
INA devices can be accessed from processor through Main I2C2 instance. Also, there is an option to
Monitor the SoC and peripheral powers using external I2C Master.
Common processor has five-pin header (J12) with isolation circuit to interface the INA devices with
external I2C Master. Buffer IC SN74CB3Q3125PWR (U69) is used to isolate the External I2C connections
from the INA devices. The control of this buffer is provided from SYS_PWR_PG, which is enabled by
default on power up.
External Power Monitor header details:
Mfr. Part# 68002-205HL (CON HDR 1X5 2.54MM PITCH ST TH)
Table 23. External Power Monitor Header Pinouts
Header (J12) Pin Number Signal Name
1 CON_PM1_SCL
2 CON_PM1_SDA
3 DGND
4 CON_PM2_SDA
5 CON_PM2_SCL
Test automation header on the Common processor board also can access these INA devices externally.
4.6 Reset
Figure 22 shows the J721E EVM reset architecture.
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