Texas Instruments Jacinto7 J721E - EVM Reset Architecture

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J721E EVM Hardware Architecture

SPRUIS4A–December 2019–Revised May 2020

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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)

Figure 22. EVM Reset Architecture

Main Page

Table of Contents1
Introduction5
- Key Features5
- Thermal Compliance6
Thermal Caution6
- REACH Compliance7
J721E EVM Board7
J721E EVM Overview7
System Architecture Interface8
- J721E EVM Board Identification9
J721E EVM Board Identification (SOM, CPB, QP Ethernet)9
- J721E SOM Component Identification10
- Jacinto7 Common Processor Components Identification11
Jacinto7 Common Processor Component Identification11
- Quad Ethernet Components Identification12
Quad Ethernet Component Identification12
EVM User Setup/Configuration13
- Power Requirements13
Connector Used for Power Input13
Recommended External Power Supply13
- Power on Switch and Power Leds14
Power ON/OFF Switch14
Power On/Fault Leds15
Power LED Status15
Power Status Leds16
Power Leds16
Power Test Points17
- EVM Reset/Interrupt Push Buttons18
EVM Push Buttons18
- EVM DIP Switches19
EVM Configuration DIP Switch19
EVM Configuration Switch Function20
EVM Configuration Switch Function21
BOOT Switches Provided on the Processor Card22
Wakup Boot Mode Switch (SW9)22
Main Boot Mode Switch (SW8)22
- EVM UART/COM Port Mapping23
UART Port Mapping23
- JTAG Emulation24
JTAG Mux24
JTAG 1:2 Mux Selection24
TI 60 Pin Connector (J16) Pinout25
Cti20 Pin Connector (J1-Refer PROC081E2 SCH) Pinout26
TI14 Pin Connector (J2-Refer PROC081E2 SCH) Pinout26
J721E EVM Hardware Architecture27
- J721E EVM Hardware Top Level Diagram27
J721E EVM Functional Block Diagram27
Quad Port Ethernet Expansion Functional Block Diagram28
- J721E EVM Interface Mapping29
- I2C Address Mapping30
J721E EVM I2C Table30
- GPIO Mapping31
J721E Soc - GPIO Mapping Table31
- Power Supply32
J721E SOM Power Distribution Block Diagram32
Power on Sequencing33
Voltage Supervisor Circuit34
LPDDR4 IO Voltage Selection Circuit35
DDR I/O Voltage Selection35
J721E Soc S2R Logic Flow36
INA Devices I2C Slave Address37
- Reset38
External Power Monitor Header Pinouts38
EVM Reset Architecture39
- Clock40
EVM Clock Architecture40
J721E Soc Primary Clock41
Processor's Secondary/Serdes Ref Clock42
EVM Peripheral Ref Clock42
- Memory Interfaces43
J721E Som LPDDR443
J721E Som OSPI and Hyper Flash44
UFS Memory Block Diagram45
Emmc Memory Block Diagram46
Micro-SD Card Block Diagram47
Board ID Memory Header Information48
- MCU Ethernet Interface49
MCU Gigabit Ethernet Block49
MCU Ethernet PHY Settings50
- 4.10 QSGMII Ethernet Interface51
Clock Source Selection51
Quad-SGMII Board I2C52
- 4.11 Pcie Interface53
QSGMII Ethernet PHY Settings53
Pcie Interface for SERDES054
Pcie SMBUS Block Diagram54
Reference Clock Selection for Pcie Host Operation55
Reference Clock Selection for Pcie Endpoint Operation55
USB2.0 Header Connection56
Resistors for Selecting Pcie Card Host or Device Operation56
Pcie Interface for SERDES157
Resistors for Selecting Pcie Card Host or Device Operation58
- 4.12 USB Interface59
Reference Clock Selection for Pcie Host Operation58
Reference Clock Selection for Pcie Endpoint Operation58
Pcie Interface for SERDES259
USB3.1 Type C Interface60
Type C Power Delivery Current Settings60
USB Hub Reference Clock Circuit61
USB Hub Settings Circuit61
USB1 ID Setting for HUB61
- 4.13 CAN Interface62
MCU CAN0 Interface62
CAN Wake Push Button63
CAN Header Connections to Db9/Test Instrument64
- FPD Interface (Audio Deserializer)65
FPD-Link UB926 ID Setting Circuit65
FPD-Link UB926 Mode Selection Circuit65
- FPD Panel Interface (DSI Video Serializer)66
FPD Audio Deserializer HSD Connector Pinout66
DSI to FPD Serializer HSD Connector Pinout66
- 4.16 Display Serial Interface (DSI) FPC67
- 4.17 Audio Interface67
FPD-Link UB981 Device Settings Circuit66
MCASP/TRACE - 1:3 MUX: Truth Table67
Config Table67
Audio Port Interface Assignment68
- 4.18 Display Port Interface69
- 4.19 MLB Interface69
Display Port Block Diagram69
MLB Header Pinout70
- 4.20 I3C Interface71
- 4.21 ADC Interface71
MLB Interface Connector70
MCU I3C Header J33 Pinout71
MAIN I3C Header J32 Pinout71
- 4.22 RTC Interface72
ADC Interface Connector71
ADC Header J23 Pinout72
- 4.23 Apple Authentication Header73
RTC Block Diagram72
APPLE AUTH Header J9 Pinout73
Apple Authentication Block Diagram73
4.24 EVM Expansion Connectors74
APPLE AUTH Footprint U108 Pinout74
Expansion Board Interface Connectors74
EVM Expansion Connector J46 Pinout75
EVM Expansion Connector J51 Pinout77
- 4.25 ENET Expansion Connector78
ENET Expansion Board Power Test Points78
CDCI I2C Isolation Circuit79
ENET Expansion Connector J10 Pinout80
- 4.26 CSI Expansion Connector82
Dual I/O Voltage Selection for CSI Expansion Interface82
CSI Expansion Connector J52 Pinout83
CSI Expansion Connector J48 Pinout83

Texas Instruments Jacinto7 J721E - EVM Reset Architecture

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