Texas Instruments Jacinto7 J721E User Manual

J721E EVM Hardware Architecture www.ti.com
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SPRUIS4A–December 2019–Revised May 2020
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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
4.25.3 Reset Signals
QSGMII_RESETz is a reset signal sourced from Common Processor board. This signal is used to reset
the QSGMII PHY on the board.
QSGMII_RESETz is an AND output of SOC_PORz_out and ENET_EXP_RSTz . The ENET_EXP_RSTz
signal is asserted by an I2C GPIO Expander2 (I2C ADD# 0x22, I2C0) Port21 in the common processor
board.
Table 47 lists the ENET expansion connector pinouts.
Table 47. ENET Expansion Connector J10 Pinout
ENET Expansion connector Interface J10
Pin No Signal
1 DGND
2 NC
3 NC
4 DGND
5 NC
6 NC
7 DGND
8 NC
9 NC
10 DGND
11 VSYS_IO_3V3
12 VSYS_IO_3V3
13 DGND
14 EEPROM_A0
15 EEPROM_A1
16 EEPROM_A2
17 DGND
18 EEPROM_WP
19 REFCLK_25MHZ
20 DGND
21 WKUP_I2C0_SCL
22 WKUP_I2C0_SDA
23 DGND
24 I2C0_SCL
25 I2C0_SDA
26 DGND
27 VCC_12V0
28 VCC_12V0
29 DGND
30 ENET_EXP_PWRDN
31 QSGMII_INTN
32 DGND
33 QSGMII4_TX_P
34 QSGMII4_TX_N
35 DGND
36 QSGMII4_RX_P
37 QSGMII4_RX_N
38 DGND
39 QSGMII_PHY_REFCLK_N

Texas Instruments Jacinto7 J721E Specifications

General

Brand	Texas Instruments
Model	Jacinto7 J721E
Category	Motherboard
Language	English