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J721E EVM Hardware Architecture
29
SPRUIS4A–December 2019–Revised May 2020
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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
4.2 J721E EVM Interface Mapping
Table 16 shows the J721E EVM Interface Mapping table.
Table 16. J721E EVM Interface Mapping
Interface Name Port on SoC Device Part Number
Memory – LPDDR4 DDR0 MT53D1024M32D4DT
Memory – OSPI MCU_OSPI0 MT35XU512ABA1G12-0SIT
(Channel B of 1:2 Mux TS3DDR3812RUAR)
Memory – Hyper Flash MCU_OSPI0 S71KS512SC0BHV000
(Channel C of 1:2 Mux TS3DDR3812RUAR)
Memory – Quad SPI MCU_OSPI1 MT25QU512ABB8E12-0SIT
Memory – eMMC MMC0 MTFC16GAPALBH-AAT ES
Memory – Micro SD Socket MMC1 DM3BT-DSF-PEJS
Memory – UFS UFS0 THGAF8G8T23BAIL
Memory – Board ID EEPROM WKUP_I2C0
(I2C6 for CSI Expansion)
CAT24C256WI-GT3
(CAV24C256WE-GT3 for J721E SOM)
Memory – Boot EEPROM MCU_I2C0 AT24CM01
Ethernet – RGMII MCU_RGMII1 DP83867ERGZT
Ethernet – Quad SGMII SERDES0 (SGMII2) VSC8514XMK
USB – 3.1 Type C + PD + CC Controller SERDES3 (USB0) 2012670005 + PTPS25830QWRHBTQ1 +
TUSB321RWBR
USB – 2.0 (HUB) USB1 TUSB4041IPAPR
Display Port SERDES4 (DP0) 472720001
FPD Link Panel Serializer DSI0 PDS90UB941ASRTDTQ1
FPD Link Radio Tuner McASP11 DS90UB926QSQE
Audio Codec McASP10 PCM3168APAP
PCIe – x4 Lane Socket (x1 Lane) SERDES0 (PCIe0) 10142333-10111MLF
PCI2 – x4 Lane Socket (x2 Lane) SERDES1 (PCIe1) 10142333-10111MLF
PCIe – M.2 Socket (M-Key 2280) SERDES2 (PCIe2) MDT320M01001
MLB/MLBP expansion MLB0 QSH-020-01-L-D-DP-A-K
UART Terminal (UART-to-USB) UART [0:2] & 4 FT4232HL
UART Terminal (UART-to-USB) WKUP_UART0 & MCU_UART0 FT2232HL
CAN (4x) MCU_MCAN0 TCAN1043-Q1 (W/ Wake function)
MCU_MCAN1 TCAN1042HGVD
MCAN0 TCAN1043-Q1 (W/ Wake function)
MCAN2 TCAN1042HGVD
ADC Header MCU_ADC0 TSW-110-07-S-D
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