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Texas Instruments Jacinto7 J721E User Manual

Texas Instruments Jacinto7 J721E
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J721E EVM Hardware Architecture
www.ti.com
82
SPRUIS4ADecember 2019Revised May 2020
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Copyright © 2019–2020, Texas Instruments Incorporated
Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
4.26 CSI Expansion Connector
The J721E EVM supports different application specific camera expansion boards, which includes:
Fusion1 Serial Capture Expansion
Fusion2 Serial Capture Expansion
Common processor board supports to interface with these CSI expansion boards using connector of QSH-
020-01-L-D-DP-A-K with 5 mm mating height allowing CSI Expansion to be stacked on bottom side of the
processor board.
Camera Serial Interface CSI0 and CSI1 of J721E SoC is interfaced to this CSI expansion connector J52
on the CP board. The Common Processor board supports the Auxiliary CSI expansion connector that is
reserved for CSI2 port of future J7 SoC.
Power (12 V and 3.3 V ), control GPIOs and reference clock to these CSI expansion boards are provided
from Common Processor board through CSI expansion connector. Optionally auxiliary 12 V can be
supplied from Common Processor board via terminal block (1757242) using external wire.
The I/O supply to these CSI expansion boards can be configured for both 3.3 V and 1.8 V using the DIP
Switch SW3 Position 7.
CSI_VIO_SEL
Sets I/O voltage for CSI2 Expansion Interface (LVCMOS signals)
‘0’ (OFF) = 1.8 V I/O Voltage
‘1’ (ON) = 3.3 V I/O Voltage
Figure 60. Dual I/O Voltage Selection for CSI Expansion Interface

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Texas Instruments Jacinto7 J721E Specifications

General IconGeneral
BrandTexas Instruments
ModelJacinto7 J721E
CategoryMotherboard
LanguageEnglish

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