J721E EVM Hardware Architecture
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SPRUIS4A–December 2019–Revised May 2020
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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
4.8.2 OSPI Interface
The J721E SOM has 512 Mbit OSPI memory device of part number MT35XU512ABA1G12-0SIT
connected to OSPI0 interface of J721E processor. The OSPI interface supports single and double data
rates with memory speed up to 166 MHz SDR and 200 MHz DDR.
The SOM board also supports an option to include Hyper Flash + Hyper RAM Mfr. Part# S71KS512SC0,
which is a 512 Mb flash + 64 Mb DRAM. 12-bit Active mux TS3DDR3812RUAR is provided to select either
OSPI or HBMC interface. The selection of OSPI and hyper flash will be done by using a DIP (SW3) switch
that is populated on the CP board. For more information, see Section 3.4.1.
Figure 26. J721E SoM OSPI and Hyper Flash
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