Texas Instruments Jacinto7 J721E - Pcie Interface for SERDES0; Pcie SMBUS Block Diagram

PCIe x2 Lane
Socket
I2C MUX
TCA9543A
PCIe x1 Lane
Socket
3.3 V
J8
U15
3.3 V
J11
SOC_I2C0_SDA
SOC_I2C0_SCL
I2CADD: 0x70
J721E EVM Hardware Architecture www.ti.com
54
SPRUIS4A–December 2019–Revised May 2020
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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
Figure 34. PCIe Interface for SERDES0
Figure 35. PCIe SMBUS Block Diagram