J721E EVM Hardware Architecture
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SPRUIS4A–December 2019–Revised May 2020
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Jacinto7 J721E/DRA829/TDA4VM Evaluation Module (EVM)
Table 44. EVM Expansion Connector J46 Pinout (continued)
INFO/GESI Connector Interface J46
Pin No Signal Pin No Signal
91 PRG0_RGMII2_TX_CTL 92 MCASP6_ACLKR/PRG1_RGMII1_RX_CTL
93 MCASP2_AXR0/PRG0_RGMII2_TD3 94 MCASP6_AXR0/PRG1_RGMII1_RD2
95 DGND 96 DGND
97 MDIO0_MDC 98 PRG0_MDIO0_MDC/I2C5_SDA
99 MDIO0_MDIO 100 PRG0_MDIO0_MDIO/I2C5_SCL
101 SPI3_D0 102 MCASP0_AXR13/PRG0_PWM0_B2
103 SPI3_D1 104 NC
105 SPI3_CLK 106 RGMII_REFCLK
107 DGND 108 DGND
109 I2C0_SCL 110 MCASP1_ACLKX
111 I2C0_SDA 112 SOC_I2C2_SCL
113 I2C1_SCL 114 SOC_I2C2_SDA
115 I2C1_SDA 116 NC
117 NC 118 EXP_RSTz
119 DGND 120 DGND
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