Chapter 4 _____________________________________________________ TTY Nonvolatile Setups
VAISALA______________________________________________________________________ 107
reception, but this can be increased to 5 MBytes if "UDP acquisition ID
mismatch" errors are ever seen in the RVP900 diagnostic log.
Limits: 100000 to 5000000 bytes
IFD synthesized system clock: 72.0000000 MHz
This is the frequency of the acquisition sampling clock in the IFDR
module. The clock is synthesized on-board using a specialized low-jitter
PLL that allows any frequency to be generated merely by choosing it here
to the nearest 0.1 Hz.
Limits: 50 MHz to 100 MHz
IFD clock is derived from an external reference: YES
External input reference: 10 MHz
The synthesized system clock can be derived from an internal crystal
oscillator or from an externally applied reference clock. When the external
source is used, its frequency is specified here.
Live angle input – 0:None, 1:SimRVP, 2:SimIFD, 3:TAGs, 4:S/D,
5:RtCtrl : 0
This setting is used to configure the input of live antenna angles. If angle
data are supplied outside of the RVP900, e.g., by and RCP8 making direct
calls to the IRIS antenna library, then select None. For test purposes, the
SimRVP and SimIFD options implement an antenna simulator either in the
host computer or the remote IFDR. Parallel angle inputs can be used
through TAGs, and 3-wire synchros can hookup using the S/D option.
Lastly, RtCtrl should be selected when custom software has been written
to deduce antenna angles from the real–time state machine controller.
TAG bits to invert AZ:0000 EL:0000
TAG scale factors AZ:1.0000 EL:1.0000
TAG offsets (degrees) AZ:0.00 EL:0.00
If you have selected TAGs, then you have these options. The incoming
TAG input bits may be selectively inverted through each of the 16-bit
words. The values are displayed in Hex. Setting a bit causes the
corresponding AZ (bits 0–15) or EL (bits 16–31) lines to be inverted. Note
that the SOPRM command also specifies TAG bits to invert. Both
specifications are XOR’ed together to yield the net inversion for each TAG
line.
The overall operations are performed in the order listed. Incoming bits are
first inverted according to the two 16-bit XOR masks. This yields an
unsigned 16-bit integer value which is then multiplied by the signed scale
factor. The result is interpreted as a 16-bit binary angle (in the low sixteen
bits), to which the offset angle is finally added.
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