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Vaisala RVP900 User Guide
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M211322EN-J
User Guide
R
VP900 Digital Rec
eiv
er and Signal Pr
oc
essor
R
VP900
2
Table of Contents
Default Chapter
3
Table of Contents
3
1 About this Document
15
Version Information
15
Related Documents
15
Table Document Versions
15
Table 2 Weather Radar Documentation
15
Documentation Conventions
16
Trademarks
16
2 Product Overview
17
RVP900 Product Architecture
17
Regulatory Compliances
18
WEEE Compliance
18
Rohs Compliance
18
Safety
20
ESD Protection
21
Product Nomenclature
21
Table 3 RVP900 Nomenclature
21
3 Functional Description
23
RVP901 if Digital Receiver
23
RVP901 IFDR Data Capture and Timing
24
Figure 2 if to I/Q Processing Steps
24
RVP901 IFDR if to I and Q Processing
25
Digital Receiver Function
25
Figure 3 Calibration Plot for RVP901
27
Table 4 Real-Time Signal Corrections to I/Q Samples
28
Figure 4 Digital if Band Pass Design Tool
29
Figure 5 Burst Pulse Alignment Tool
30
Digital Transmitter Function
31
Figure 6 Received Signal Spectrum Analysis Tool
31
Table 5 Example Tx/Rx Processing Algorithms
32
Magnetron Receiver Example
33
Figure 7 Analog Vs Digital Receiver for Magnetron Systems
33
Figure 8 Basic Magnetron System
35
Figure 9 Dual Polarization Magnetron System
36
Klystron or TWT Receiver and Transmit RF Example
37
Figure 10 Analog Versus Digital Receiver for Klystron Systems
37
RVP902 Signal Processing Computer
38
Figure 11 Klystron System with Digital Tx
38
LAN Connection for Data Transfer or Parallel Processing
39
Open Hardware and Software Design
39
RVP902 Socket Interface
39
RVP902 Socket Protocol
40
Table 6 Socket Protocol Commands
40
Public API
42
RVP900 Weather Signal Processing
42
Table 7 API Support for Modifying Signal Processing
42
Figure 12 I/Q Processing for Weather Moment Extraction
43
Burst Pulse Analysis for Amplitude, Frequency, and Phase
44
Figure 13 Burst Pulse Analysis for Amplitude/Frequency/Phase
44
TAG Angle Samples of Azimuth and Elevation
45
Time (Azimuth) Averaging
45
Moment Extraction
46
Range Averaging and Clutter Microsuppression
46
Speckle Filter
46
Threshold Processing
46
Autocorrelations
47
Table 8 Example Unambiguous Velocity Intervals
47
Velocity Unfolding
47
Table 9 Autocorrelation Mode
48
Output Data
49
Radar Control Functions
50
Table 10 Radar Control Functions
50
Configuration and Monitoring
51
Figure 14 Reset IP Address
51
Digital AFC (DAFC)
52
Expansion Panels
52
Utilities and Applications
52
Table RVP Utilities
52
Network Architecture
53
Table 12 Radar Application Software
53
Figure 15 Network Architecture
54
4 RVP Hardware
55
Hardware System Overview
55
RVP901 IFDR Hardware
56
Figure 16 RVP900 System Concept
56
Upgrading if Receiver with RVP901 IFDR
57
RVP901 IFDR Power, Size, and Mounting Considerations
58
Table 13 IFDR Installation Considerations
58
RVP901 IFDR I/O Connectors
59
Table 14 RVP901 Connector Panel Summary
59
Table 15 Generic Interconnect Cable for IFDR Analog/Digital I/O
60
RVP901 Miscellaneous Discrete and Analog I/O Connectors
62
Table 16 Discrete and Analog I/O
62
Table 17 RVP901 51-Pin Micro-D Summary
62
RVP901 IFDR Status Indicators
63
Table 18 RVP901 IFDR LED Indicators
63
Defining RVP901 IFDR Input A/D Saturation Levels
64
RVP901 IFDR Inputs
64
Table 19 RVP901 IFDR Input Options
64
Configuring the RVP901 IFDR Clock Subsystem
65
Table 20 Clock Generator
65
Table 21 Clock Generator Concerns in a Synchronous Radar System
66
Table 22 Sample Clock Frequency Considerations
67
Configuring External Pre-Trigger Input
68
IF Bandwidth and Dynamic Range
69
Figure 18 Calibration Plot for a Stand-Alone 16-Bit IFDR
70
Configuring if Gain Based on System Performance
71
Figure 19 Trade-Off between Dynamic Range and Sensitivity
71
Configuring if Gain Based on System Noise Figure
73
Choosing Intermediate Frequency
74
Installing RVP902 Main Chassis
75
Powering-Up RVP902
75
Installing DAFC
76
Figure 20 DAFC Module
76
Figure 21 DAFC Assembly Diagram
77
Table 23 DAFC Protocol Jumper Selections
78
Example: Hookup to a CTI MVSR-XXX STALO
79
Table 24 Pinout for the CTI MVSR-XXX STALO
79
Example: MITEQ MFS-05.00- 05.30-100K-10MP STALO
81
Table 25 Pinout for the MITEQ MFS-XX.XX-XX.XX-100K-Xxmp Synthesizers
81
Using the Legacy IFD Coax Uplink
82
Figure 22 Recommended Receiving Circuit for the Coax Uplink
83
Figure 23 Timing Diagram of the IFD Coax Uplink
83
Table 26 Bit Assignments for the IFDR Coax Uplink
84
Table 27 Digital AFC Pinmap Commands
86
5 TTY Non-Volatile Setups
89
Using the TTY Setup Menu
89
Factory, Saved, and Current Settings
90
Table 28 Settings Commands
90
And Vz - View Card and System Status
91
Vp - View Processing and Threshold Values
93
Displaying and Changing Current Major Mode
94
Managing Settings with M Menus
94
Mb - Burst Pulse and AFC
95
Table 29 Analysis Window Options
97
Table 30 AFC Output Process for Internal AFC Feedback
100
MC - Top-Level Configuration
104
Mf - Clutter Filters
106
Mp - Processing Options
109
Mt - General Trigger Setups
115
Mt<N> - Triggers for Pulsewidth N
118
Table 31 PRF Protection Limits Considerations
120
Table 32 Filter Length Considerations
121
Table 33 Linear FM Class Examples
127
Mz - Transmissions and Modulations
128
M+ Debug Options
129
6 Plot-Assisted Setups
131
Plot-Assisted Setup Overview
131
Plot Command Conventions
131
Configuring RVP900 Digital Front End
132
Table 34 Plot Command Conventions
132
P+ - Plot Test Pattern
133
Pb - Plot Burst Pulse Timing
134
Interpreting the Burst Timing Plot
134
Figure 24 Test Pattern Display
134
Figure 25 Successful Capture of the Transmit Burst
135
Pb Subcommands
136
TTY Information Lines in Pb
137
Table 35 Pb Subcommands
137
Adjusting Burst Pulse Timing
138
Table 36 Pb TTY Information Lines
138
Ps - Plot Burst Spectra and AFC
139
Interpreting Burst Spectra Plots
139
Figure 26 Example of a Filter with Excellent DC Rejection
140
Figure 27 Example of a Filter with a Poorly Matched Filter
141
Ps Subcommands
142
Table 37 Ps Subcommands
143
TTY Information Lines Within Ps
144
Table 38 Ps TTY Information Lines
145
Computing Filter Loss
146
Adjusting Plot Burst Spectra and AFC
149
Figure 28 Example of a Poorly Matched Filter
150
Figure 29 Example of a Filter with Poor DC Rejection
152
Using AFC Test Mode
153
Plotting Example for Pulse Width Definition, Waveform, and Filters
154
Plotting Example for Range Resolution Ambiguity
156
Pr - Plot Receiver Waveforms
157
Interpreting Receiver Waveform Plots
157
Figure 30 Example of Combined if Sample and LOG Plot
158
Figure 31 Example of a Noisy High Resolution Pr Spectrum
159
Available Subcommands in Pr
160
Table 39 Pr Subcommands
160
TTY Information Lines in Pr
161
Table 40 Pr TTY Information Lines
161
Pa - Plot Tx Waveform Ambiguity
162
Interpreting Ambiguity Plots
162
Figure 32 Ambiguity Diagram of a Compressed Tx Pulse
163
Available Subcommands in Pa
164
Figure 33 Frequency, Phase and Amplitude of a Compressed Tx Pulse
164
Table 41 Pa Subcommands
165
TTY Information Lines in Ps
166
Table 42 Ps TTY Information Lines
166
Bench Testing Compressed Waveforms
167
Figure 34 IFDR Sampling of Optimized Compressed Tx Waveform
168
Figure 35 Ideal and Actual Linear -FM Spectrum Displayed in Ps Plot
169
7 Processing Algorithms
171
RVP Algorithm Overview
171
Measured Quantities
172
Table 43 Algebraic Quantities Within the RVP900 Processor
172
IF Signal Conversion Process
173
IF Signal Processing
174
FIR (Matched) Filter
174
Figure 36 RVP 900Processing Flow Diagram
174
RVP900 Receiver Modes
176
Table 44 Receiver Mode Configuration Options
176
Automatic Frequency Control (AFC)
178
Burst Pulse Tracking
179
Interference Filter
180
Table 45 Algorithm Results for +16 Db Interference
181
Table 46 Impact of False Alarms on Reflectivity Estimates
181
Table 47 Algorithm Results for +26 Db Interference
182
Large-Signal Linearization
183
Amplitude Correction for Tx Power Fluctuations
184
Figure 37 Linearization of Saturated Signals above +8 Dbm
184
Time Series Signal Processing
185
Time Series and Doppler Power Spectrum Example
186
Table 48 Supported Time Series Processing Modes
186
Frequency Domain Processing- Doppler Power Spectrum
187
Figure 38 Time Series and Doppler Power Spectrum Example
187
Figure 39 Typical Form of Time Series Window
188
Autocorrelation for Moment Estimations
189
Figure 40 Impulse Response of Typical Window
189
Table 49 Time Domain Calculation of Autocorrelations and Corresponding Physical Models
190
Ray Synchronization on Angle Boundaries
191
Clutter Filtering Approaches
191
Table 50 Clutter Filtering in Major Modes
191
Figure 41 Fixed Width Clutter Filter Examples
193
Figure 42 Variable Width Clutter Filter
194
Figure 43 GMAP Algorithm Steps
196
Table 51 GMAP Algorithm Steps
196
Autocorrelation R(N) Processing
201
Point Clutter Remover
201
Figure 44 GMAP Example
201
Range Averaging and Clutter Microsuppression
202
Reflectivity
202
Table 52 Terms in the Db Equation Format
203
Velocity
205
Spectrum Width Algorithms
206
Signal Quality Index (SQI Threshold)
207
Clutter Correction (CCOR Threshold)
207
Weather Signal Power (SIG Threshold)
208
Table 53 SIG Calculation
208
Signal+Noise) to Noise Ratio (LOG Threshold)
209
Thresholding
209
Threshold Qualifiers
209
Table 54 Threshold Quality Criteria
209
Table 55 Threshold Qualifiers
210
Adjusting Threshold Qualifiers
211
Table 56 Default Threshold Combinations
211
Table 57 Adjusting Threshold Qualifiers
211
Speckle Filter Processing
212
Figure 45 1D Speckle Filtering Algorithm
213
Table 58 1D Speckle Filters
213
Table 59 2D 3X3 Speckle Filter Rules
214
Figure 46 2D 3X3 Filtering Concept Examples
215
Reflectivity Calibration
216
Plot Method for Calibration of Io
216
Figure 47 Model Intensity Curve - Power at Antenna Feed (2Db Per Major Division)
217
Single-Point Direct Method for Calibration of I O
219
Treatment of Losses in Calibration
220
Figure 48 Overview of Losses that Affect LOG Calibration
220
Determining Dbzo
221
Dual PRT Processing Mode
222
Table 60 Radar Parameters
222
DPRT-1 Mode
223
DPRT-2 Mode
224
Dual PRF Velocity Unfolding
224
Figure 49 Dual PRF Concepts
226
Random Phase Second Trip Processing
228
Figure 50 Example of Dual PRF Trigger Waveforms
228
Random Phase Second Trip Processing Algorithm
229
Figure 51 Random Phase Processing Algorithm
230
Tuning for Optimal Performance
231
Signal Generator Algorithm Testing
233
Linear Ramp of Velocity with Range
233
Verifying PHIDP and KDP
234
Verifying RHOH, RHOV, and RHOHV
234
8 Host Computer Commands
237
Host Computer Command Overview
237
Setting-Up Data Acquisition and Processing
237
First-In-First-Out (FIFO) Buffer
238
Operation (NOP)
239
Load Range Mask (LRMSK)
239
Table 61 LRMSK Parameters
239
Setup Operating Parameters (SOPRM)
241
Table 62 SOPRM Threshold Options
242
Table 63 Topmode Bits
245
Table 64 RVP Clutter Filter Controls
245
Table 65 Example Flag Values with Acceptance Criteria Combinations
247
Interface Input/Output Test (IOTEST)
252
Table 66 Default Values for Melting Height Operating Parameters
252
Interface Output Test (OTEST)
253
Sample Noise Level (SNOISE)
254
Initiate Processing (PROC)
257
Table 67 PROC Modes
258
Table 68 PROC 8-Bit and 16-Bit Data Formats
260
Table 69 TSOUT Random Phase Major Mode Values
266
Load Clutter Filter Flags (LFILT)
270
Get Processor Parameters (GPARM)
273
Table 70 RVP900 Status Output Words
273
Load Simulated Time Series Data (LSIMUL)
291
Reset (RESET)
294
Define Trigger Generator Waveforms (TRIGWF)
295
Define Pulse Width Control and PRT Limits (PWINFO)
296
Set Pulse Width and PRF (SETPWF)
298
Load Antenna Synchronization Table (LSYNC)
299
Figure
301
Set or Clear User LED (SLED)
302
TTY Operation (TTYOP)
302
Load Custom Range Normalization (LDRNV)
305
Read Back Internal Tables and Parameters (RBACK)
306
Table 71 Data Returned by RBACK
306
Pass Auxiliary Arguments to Opcodes (XARGS)
308
Load Clutter Filter Specifications (LFSPECS)
309
Configure Ray Header Words (CFGHDR)
310
Configure Interference Filter (CFGINTF)
312
Set AFC Level (SETAFC)
313
Set Trigger Timing Slew (SETSLEW)
314
Hunt for Burst Pulse (BPHUNT)
314
Configure Phase Modulation (CFGPHZ)
315
Set User IQ Bits (UIQBITS)
316
Set Individual Thresholds (THRESH)
317
Set Task Identification Information (TASKID)
319
Define PRF Pie Slices (PRFSECT)
321
Configure Target Simulator (TARGSIM)
323
Set Burst Pulse Processing Options (BPOPTS)
325
Custom User Opcode (USRINTR and USRCONT)
325
Load Melting Layer Specification (MLSPEC)
326
9 Technical Data
331
Signal Processing
331
RVP900 Processing Algorithms
331
Table 72 Signal Processing
331
Table 73 Processing Algorithms
331
RVP900 Input and Output Summary
332
Table 74 I/O Summary
332
RVP901 IFDR Specifications
333
Table 75 if Band Pass Filter
333
Table 76 if Inputs
333
Table 77 Phase Stability
334
Table 78 if Waveform Generator
334
Table 79 RVP901 IFDR I/O
334
RVP901 Digital Waveform Synthesis
335
Table 80 RVP901 IFDR Physical Specifications
335
Table 81 Digital Waveform Synthesis
335
RVP902 Signal Processing Computer Specifications
336
Table 82 Physical and Environmental Characteristics
336
RVP902 Safety Compliance
337
Table 83 RVP902 Safety Compliance
337
RVP900 Spare Parts
338
Physical and Environmental Characteristics
338
Table 84 RVP900 Spare Parts
338
Table 85 RVP902-IO Spare Parts
338
Table 86 Physical and Environmental Characteristics
338
Type Plate
339
Figure 52 RVP902 Type Plate
339
Figure 53 RVP902-IO Type Plate
340
Appendix A: Installation and Test Procedures
341
Installation and Test Procedure Overview
341
Test Checklist
342
Table 87 RVP Test Checklist
342
Installation Check
343
Table 88 RVP Installation Checklist
343
Power up Check
344
Table 89 Power up Checklist
344
Terminal Setup Check
345
Table 90 Terminal Set up Checklist
345
Checking Terminal Setup
346
Checking Internal Status with Setup V Command
346
Checking Board Configuration with Setup MC Command
347
Table 91 Internal Status Setup Checklist
347
Table 92 Board Configuration Checklist
347
Checking Processing Options with Setup Mp Command
348
Table 93 Processing Options Setup Checklist
348
Checking Clutter Filters with Setup Mf Command
349
Checking General Trigger Setup with Setup Mt Command
349
Table 94 Clutter Filters Setup Checklist
349
Initial Setup of Information for each Pulse Width
351
Table 95 General Trigger Setup Checklist
351
Checking Burst Pulse and AFC with Setup Mb Command
352
Table 96 Pulse Width Information Checklist
352
Checking Debug Options with the M+ Command
353
Table 97 Burst Pulse and AFC Set up Checklist
353
Checking Transmitter Phase Control with Setup Mz Command
354
Table 98 Debug Options Checklist
354
Ascope Test
355
Table 99 Transmitter Phase Control Setup Checklist
355
Burst Pulse Alignment
356
Table 100 Ascope Setup Checklist
356
Bandwidth Filter Adjustment
357
Table 101 Burst Pulse Alignment Checklist
357
Digital AFC (DAFC) Alignment (Optional)
358
Table 102 Bandwidth Filter Setup Checklist
358
Table 103 DAFC Setup Checklist
359
MFC Functional Test and Tuning (Optional)
360
AFC Functional Test (Optional)
361
Table 104 MFC Setup Checklist
361
Checking Input if Signal Level
362
Table 105 AFC Setup Checklist
362
Table 106 Input if Signal Level Setup Checklist
363
Checking Calibration and Dynamic Range
364
Checking Receiver Bandwidth
365
Table 107 Calibration and Dynamic Checklist
365
Figure 54 Total Power and if Frequency
366
Checking Receiver Phase Noise
367
Table 108 Receiver Bandwidth Checklist
367
Hardcopy and Backup of Final Setups
368
Table 109 Receiver Phase Noise Checklist
368
RVP901 Txdac Stand-Alone Bench Test
369
Table 110 Backup and Hardcopy Checklist
369
Table 111 RVP901 Txdac Stand-Alone Bench Test Checklist
370
Appendix B: RVP901 IFDR Technical Drawings
371
Figure 55 RVP901 IFDR - Top and Front Face
371
Figure 56 RVP901 IFDR - Right and Left Sides
372
Figure 57 RVP901 IFDR - Fan Side (Heat Sink)
372
Appendix C: RVP900 Developer Notes
373
Customizing RVP Software
373
RVP Code Organization
373
Table 112 RVP Hardware and Software Organization
373
Figure 58 RVP Hardware and Software Organization
375
RVP Software Maintenance Model
375
Table 113 Software Maintenance Model
375
Building a Customised RDA Tree
376
Debugging and Profiling Your Code
376
Monitoring Opcode/Data Activity: -Exposeio
376
Showing Live Acquired Pulse Information: -Showaq
377
Showing Coherent Processing Intervals: -Showcpis
378
Showing Realtime Callback Timers: -Showrtctrl
379
Using DDD on Main and Proc Code
381
Finding Memory Leaks with Valgrind
382
Profiling with Gprof
383
Creating New Major Modes from Old Ones
384
Function Pointers for Customization
385
Table 114 Summary of Customization Methods
385
Real-Time Control of RVP
386
Using Programmable Callback Timers
386
Standard Trigger and Antenna Event Example
387
Using the Intel IPP Library
388
Appendix D: Time Series Recording
391
Time Series Overview
391
TS Record and Playback Software Architecture
391
Table 115 Time Series Software Components
391
Figure 59 IQ Data Recording/Playback General Case
392
Table 116 Description of IQ Data Recording/Playback General Case
392
Using RVP Timeseries API
393
Reader and Writer Clients
393
Attach and Detach Details
394
Extracting Pulses with Sequence Numbers
394
Using Memory Bandwidth Effectively
394
Installing and Configuring TS Recording
395
Required Software for TS Recording
395
Configuring UDP Ports for TS Recording
395
Table 117 Required Software for TS Recording
395
Configuring Automatic Startup of Tsimport and Tsexport
396
Configuring Network Buffering for Tsimport
396
Table 118 Recommended UDP Ports for TS Recording
396
Running Tsimport and Tsexport from the Command Line
397
TS Switch Utility
397
Figure 60 TS Switch Utility
397
TS Archive Utility
398
Table 119 TS Switch Status Indicators
398
Figure 61 TS Archive Utility
399
Software Application Examples
402
RVP900 in Normal Real-Time Operation
403
Figure 62 RVP900 in Normal Real-Time Operation
403
TS Recording on a Local RVP900
404
TS Recording on Separate Archive Host
404
Figure 63 TS Record on Local RVP900
404
Figure 64 TS Record on Separate Archive Host
405
TS Playback on a Local RVP900
406
Figure 65 TS Playback on Local RVP900
406
TS Playback from a Separate Archive Host to an RVP900
407
Figure 66 TS Playback from a Separate Archive Host
407
TS Archive Recording Quick Guide
408
TS Archive Playback Quick Guide
408
Ascope Playback Features
408
Figure 67 Ascope Differences During RVP900 TS Playback
409
Archive on Local RVP900
410
Archive on Separate Archive Host
410
TS Playback Using IRIS
410
Table 120 Configuration Requirements for IRIS Playback
410
TS View Utility
411
Starting Tsview
412
Starting Tsview Sample Session
412
Tsview Command Line Options
413
TS Record Data Format
415
Table 121 TS File Format
415
Appendix E: Serial Status Formats
419
Table 122 Internal BITE Packet (RVP900 to Host)
419
Table 123 Internal QBITE Packet (RVP900 to Host)
424
Appendix F: Softplane.conf
425
Configuring the Softplane.conf File
425
Softplane.conf Organization and Syntax
425
Testing, Backup, and Calibration
429
Appendix G: RCP903 ASR9-WSP Panel
431
ASR9-WSP with RCP903 ASR9-WSP Panel Overview
431
RCP903 ASR9-WSP Panel Regulatory Compliances
431
Table 124 RCP903 ASR9-WSP Panel Regulatory Compliances
431
Power Conditions for Use - RCP903 ASR9-WSP
432
ASR9 WSP with RVP900 Panel Architecture
433
Figure 68 ASR9 WSP with RVP7 Architecture
434
Figure 69 ASR9 WSP with RVP900 Architecture
436
RVP901-WSP Signal Processor Customized for ASR9 WSP
436
Table 125 RVP900-WSP Components
436
RCP903 ASR9-WSP Custom Panel
437
RVP902-WSP Processor Customized for ASR9 WSP
437
Table 126 RVP901-WSP Customizations for ASR9 WSP
437
RCP903 ASR9-WSP Panel Physical Interfaces
438
RCP903 ASR9-WSP Panel Dimensions
438
Figure 70 Top Panel Dimensions
438
Figure 71 Side Panel Dimensions
438
Figure 72 RCP903 Front Panel Dimensions
439
Figure 73 RCP903 Back Panel Dimensions
439
Figure 74 RCP903 Panel Perspective View
439
ASR9-WSP Connector Locations
440
RCP903 Shelf
440
Figure 75 Rxnet7 Front Panel
440
Figure 76 RCP903 Rack Side Perspective View
440
Figure 77 RCP903 ASR9-WSP Panel
440
Figure 78 RCP903 Shelf
440
RCP903 ASR9-WSP Electrical Interfaces
441
RCP903 ASR9-WSP Interconnect Cabling
441
Figure 79 System Testing Boundary
441
RVP901-WSP to ASR9 Radar
442
Table 127 RVP901-WSP Interface to ASR9 Radar
442
Table 128 RVP901-WSP SMA Connector Summary
442
RCP903 ASR9-WSP Panel Interfaces
443
Figure 80 Vaisala Supplied, Bay 4
443
Table 129 RCP903 ASR9-WSP Panel Connectors Defined for Customer's Systems Implementation
443
ASR9-WSP Panel Indicators and Switches
444
J1 - ASR9 Interface WSP #1
444
Table 130 ASR9-WSP Panel Indicators and Switches
444
Table 131 Pin-Out for J1 ASR9 / WSP #1
444
J2 ASR9 Interface WSP #2
446
Table 132 Pin-Out for J2 ASR9 / WSP #2
446
J3 and J4 RS-232 Interfaces to RVP902-WSP Processor
447
J5 - Ethernet Interface
447
Table 133 Pin-Out for J3 and J4 RS-232 Serial Interface
447
Table 134 Pin-Out for J6 RJ-45 Interface
447
J6 - RVP901-WSP Misc IO a to RCP903 ASR9-WSP Panel
448
Figure 17 RVP901 IFDR
448
Table 135 RVP900 Signal Types in CBL210313
448
Table 136 CBL210313 RCP903 Interconnect Cable to RVP901-WSP Misc IO Port a (J3)
448
J7 - Power Interface (DC)
449
ASR9 RIM Software API
450
Table 137 Pin-Out for J7 Power Input
450
Table 138 RIM API Board Status Functions
450
Table 139 RIM API 6-Level Weather Functions
451
Table 140 RIM API Diagnostic IO Functions
451
Table 141 RIM API Clock Functions
452
Table 142 RIM API Azimuth Functions
452
Table 143 RIM API STC Functions
452
Table 144 RIM API Data Processing Controls
453
Table 145 RIM API Simulated Controls
453
Table 146 Deprecated Functions
454
Appendix H: TDWR Customizations
455
TDWR Technical Drawings
455
Figure 81 J1 to J9 Wiring Diagrams
455
Figure 82 J90 to J111 Wiring Diagrams
456
Figure 83 J13 Wiring Diagram
457
TDWR Custom Back Panel
458
Figure 84 Control Panel Assembly
458
Table 147 J1 Filter Amp #1
459
Table 148 J2 Filter Amp #2
459
Table 149 J3 Pedestal
459
Table 150 J4 Transmitter
460
Table 151 J5 STC #1
460
Table 152 J6 STC #2
460
Table 153 J7 Stability Monitor
460
Softplane.conf File: RVP900 TDWR Panel Example
461
Table 154 J8 REX Power
461
Appendix I: References and Credits
467
Glossary
469
Index
474
Hardware Limited Warranty
481
Technical Support
481
Recycling
481
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Vaisala RVP900 Specifications
General
Model
RVP900
Storage Temperature
-40 ... +70 °C
Data interface
Ethernet
Protocols
TCP/IP
Interfaces
Ethernet
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