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Vaisala RVP900 - Hardware Installation; Overview and Input Power Requirements

Vaisala RVP900
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Both inputs are on SMA connectors.
The IF signal should be driven by the front-end mixer/LNA/IF-Amp. components, similar to
how a LOG receiver would be installed. The magnetron burst pulse, or klystron COHO
reference, is also derived in the same manner as a traditional analog receiver.
IF Input and Burst Input
The A/D input saturation level for the IF input and burst input is +8 dBm.
In most installations, an external, anti-alias filter is installed on both of these inputs. These
filters (if supplied by Vaisala) are mounted externally on one side of the IFDR, and have an
insertion loss of 0.5 dB ... 1.0 dB. Thus, the input saturation level is +8.5 dBm ... +9.0 dBm,
measured at the
filter inputs.
For the burst pulse, or COHO reference, it is important not to exceed the A/D saturation
level. This reference signal should be strong enough, so that most of the bits in the A/D
converter are used eectively, but it should also allow a few decibels below the saturation
level for safety. The recommended power level is in the range -10 dBm ... +4 dBm. This is
important for making a precise phase measurement on each pulse.
See A.16 Burst Pulse Alignment (page 354).
IF Receiver Input
For the IF receiver input, it is permissible (in fact, desirable) to occasionally exceed the A/D
input saturation level at the strongest targets, however inputs must not exceed 20 dBm.
RVP900 uses a statistical linearization algorithm to derive correct power levels from targets
that are as much as 6 dB above saturation.
Establish the IF signal level by weak-signal and noise considerations, rather than by working
backwards from the saturation level.
4.2.8
Configuring the RVP901 IFDR Clock Subsystem
RVP901 IFDR provides a flexible, programmable, low jitter clock generator used in sampling
the IF inputs and generating the IF outputs.
Table 20 Clock Generator
Source Description
Master Clock Source Clock reference can be provided by a 20 MHz on-board oscillator. An external clock
reference may also be provided to RVP901 through CLK-IN (J7).
The master clock source is software-configurable between the on-board 20 MHz
reference or an external source. The external clock option allows the RVP901 IFDR to
be phase locked to a standard system reference; however, the external clock is not a
requirement.
Recommended operating frequency is 7.5 ... 100 MHz and amplitudes -20 ... 6 dBm.
The input clock has a 50 Ω input impedance.
The internal reference oscillator is a high-quality oscillator, but is not temperature
compensated. The internal 20 MHz reference frequency stability is 20 ppm over
extended temperature range of -40° ... +85°C (-40° ... +176°F). Its jitter is sub–
picosecond.
Chapter 4 – RVP Hardware
63

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