Vaisala RVP900 - Table 22 Sample Clock Frequency Considerations

Concern Description
RVP900 Receives the
Existing Radar Trigger
When an external trigger is supplied to RVP900, the processor synchronizes its
internal range bin selection circuitry to that external trigger. The placement of the
range bins themselves, however, is always synchronous with the RVP901 IFDR
selectable sampling clock. The result is that 27.8 nanoseconds of jitter is introduced
in the placement of RVP900 range bins relative to the transmitted pulse.
The eect of this synchronization jitter is that targets appear fluctuate in range by
approximately 4.2 m. Although this is small, relative to the range bin spacing, and
does not
aect the range accuracy of the data, the eect on overall system stability
is more severe. Using both numerical modeling and field measurements, we have
found that sub-clutter visibility of a μsec pulse may be limited to approximately 43
dB as a result of this 27.8 nanoseconds range jitter. This falls quite short of the usual
expectations of a synchronous radar system in which clutter rejection of 55 ... 60 dB
should be attainable.
The solution to these concerns is to provide a way for the RVP901 IFDR internal sampling
clock to be phase locked to the radar system. If RVP900 provides the radar triggers, then
those triggers become synchronous with the radar COHO. If RVP900 receives an external
trigger, then its range bin clock is synchronous with that external trigger, and there is no
synchronization jitter in the range bins.
The RVP901 IFDR can lock its sampling clock to an external system clock reference through
the CLK-IN SMA input. This results in an RVP900 that is fully synchronous with the existing
radar timing.
4.2.8.1 Choosing A/D Sample Rate or Tx Synthesis Rate
The internal system clock, which samples the IF input signals and synthesizes the Tx output
waveforms, can be configured to run at any frequency between 50 MHz ... 100 MHz.
The setup questions in the Mc menu select the sampling clock frequency and whether the
clock is derived from a stable on-board crystal oscillator or from the external CLK-IN SMA
reference. See 5.2.2 Mc — Top-level Configuration (page 102).
The sample clock frequency aects many components of the radar and signal processing
system. The choice of frequency is likely to be dierent for each radar facility, because it
represents a
trade-o of the following considerations.
Table 22 Sample Clock Frequency Considerations
Consideration Description
A/D Quantization Noise and
Dynamic Range
The inherent SNR of the A/D converter chip is spread over a Nyquist band,
whose width is determined by the sampling frequency.
See 4.2.10 IF Bandwidth and Dynamic Range (page 67).
As the sampling frequency increases, the A/D quantization noise that is
contained within a given Rx bandwidth decreases, which means that
RVP900 becomes more quiet.
The dynamic range varies linearly with sampling frequency. RVP900 has 3
dB greater dynamic range at 100 MHz versus 50 MHz clock.
Chapter 4 – RVP Hardware
65