Vaisala RVP900 - Configuring External Pre-Trigger Input

Consideration Description
Quantization of Trigger Timing
and Range Bin Placement
Triggers generated by RVP900 are specified by their start time in
microseconds, width in microseconds, and polarity. Triggers are always
produced that are ±0.5 clocks of these ideal values.
If you want the triggers to be precisely aligned down to the exact clock
edge, the sample clock frequency should be chosen so that trigger edges
fall on integer multiples of the clock period.
Similarly, the range bin spacing is specified in meters and are always within
half a clock period of the ideal value. The bins can also be placed precisely
in range, by choosing a clock period that is an integer multiple of the
desired spacing.
Maximum Length of FIR Down-
conversion Filters
The FIR filters that compute (I,Q) time series from raw IF samples must
process those samples at the acquisition clock rate. A filter of a given length
in microseconds must contain a greater number of taps (coecients) as the
sample rate increases.
For very long filters (greater than 40 μsec), it may sometimes be necessary
to limit the clock rate, in order to achieve the desired impulse response
length.
The Mt<n> and Ps menus are helpful in determining the maximum length
filter that can be achieved for a given RVP900 processing gmode (aected
by single/dual polarization, range bin spacing, and so on).
Null Frequency Bands in
Synthesized Tx Output
When RVP900 generates a synthesized Tx waveform , the output frequency
cannot be within the interval of frequencies 0.4 ... 0.6 f, where f is the
sample clock rate.
Use the RVP900 setup menus to cross-check the above constraints. Note that the system
installer must choose a sample clock frequency that achieves the best set of
trade-os at
each radar site.
4.2.9
Configuring External Pre-Trigger Input
You may supply RVP900 with your own CMOS-level pre-trigger for installations in which
adequate trigger control already exists.
1. In the softplane.conf file, configure the trigger input.
The trigger input is provided on the RVP901 IFDR TRIG-A or TRIG-B SMA connector
J8 and J15, or on a TTL or RS-422 I/O line on J3 or J6.
The trigger input threshold is 1.3 V and can tolerate a 5 V maximum input when DC
coupled. If AC coupled and 50 Ω terminated, it can take a -6 ... 8 dBm input signal. This
makes it easier to connect to existing high-voltage trigger distribution systems. The
rising or falling edge of this external trigger signal is interpreted by RVP900 as the
pretrigger point. The pulse width of the signal does not matter.
2.
Configure the delay to range0 in the TTY Setups.
See 5.2.6 Mt<n> — Triggers for Pulsewidth n (page 116).
3. Synchronize the other trigger outputs to the input trigger.
The synchronization jitter between the user pretrigger and the other trigger outputs
are less than the period of the A/D sampling clock, for example, 10 nanoseconds at a
100 MHz rate.
RVP900 User Guide M211322EN-J
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